The PCM9211 can output decoded channel status data, user data, and a validity flag synchronized with audio data from the input S/PDIF signal. These signals can be transmitted from any of the three MPIOs (MPIO_A, MPIO_B, or MPIO_C). To assign this function to the MPIOs, see the Section 7.3.8.8 section.

Each type of output data has own dedicated output pin:

• Channel status data (C) are output through MPIOs assigned as COUT.
• User data (U) are output through MPIOs assigned as UOUT.
• Validity flag (V) is output through MPIOs assigned as VOUT
• Data (left and right) are identified as DOUT.

C, U, and V output data are synchronized with the recovered LRCKO (left-right clock output) from the S/PDIF input signal.

The polarity of the recovered LRCKO from the S/PDIF input depends on the Register 2Fh/RXFMT[2:0] setting.

The beginning of each S/PDIF frame (BFRAME) is provided as one of the outputs on the MPIO. It can be used to indicate the start of the frame to the decoding DSP. If the DIR decodes a start-of-frame preamble on the decoded data, then it sets BFRAME high for 8xLRCK periods to signify the start of the frame.

LRCKO can be used as a reference clock for each of the data outputs, BFRAME, DOUT, COUT, UOUT, and VOUT. The relationship between each output is shown in Figure 7-14.

Numbers 0 to 191 of DOUT, COUT, UOUT, and VOUT in Figure 7-14 indicate the frame number of the input biphase signal.

Figure 7-14 LRCKO, DOUT, BFRAME, COUT, UOUT, and VOUT Output Timing

The RXVDLY Register in Register 22h controls when the VOUT pin goes high (either immediately, or at the start of the sample/frame). Figure 7-15 shows these timing sequences.

Figure 7-15 RXVDLY and VOUT Timing