The device interfaces up to four digital pulse-density-modulation (PDM) microphones for simultaneous conversion and uses high-order and high-performance decimation filters to generate pulse code modulation (PCM) output data that can be transmitted on the audio serial interface to the host using either time-division multiplexing (TDM), I²S, or left-justified (LJ) audio formats.

The device internally generates PDMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz, 1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz, 2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz) using the PDMCLK_DIV[1:0] (P0_R31_D[1:0]) register bits. PDMCLK can be routed on the PDMCLKx_GPOx pin. This clock can be connected to the external digital microphone device. The device also support control register to independently configure each channel PDMDINx data to be latched using either rising edge or falling edge. Figure 7-14 shows a connection diagram of the digital PDM microphones.

The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK. Internally, the device latches the steady value of the data on the rising edge of PDMCLK or the falling edge of PDMCLK based on the configuration register bits set in P0_R32_D[7:4]. Figure 7-15 shows the digital PDM microphone interface timing diagram.

Figure 7-15 Digital PDM Microphone Protocol Timing Diagram