米6体育平台手机版

ZHCSL30B June 2009 – March 2020 PGA280

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

PW|24
- MPDS363A

散热焊盘机械数据 (封装 | 引脚)

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6.2 Electrical Characteristics

at T_A = 25°C, VSP = 15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = 3 V, DGND = 0 V, R_L = 2.5 kΩ to VSOP/2 = VOCM, G = 1 V/V, using internal clock, BUF inactive, V_CM = 0 V, and differential input and output (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT
V_OS	Offset voltage, RTI⁽¹⁾	Gain = 1 V/V, 1.375 V/V			±50	±250	µV
V_OS	Offset voltage, RTI⁽¹⁾	Gain = 128 V/V			±3	±15	µV
dV_OS/dT	vs temperature⁽²⁾	T_A = –40°C to +105°C	Gain = 1 V/V		±0.2	±0.6	μV/°C
dV_OS/dT	vs temperature⁽²⁾	T_A = –40°C to +105°C	Gain = 128 V/V		±0.03	±0.17	μV/°C
PSR	vs power supply, RTI	VSP – VSN = 10 V and 36 V, gain = 1 V/V, 128 V/V			±0.3	±3	µV/V
dV_OS/df	vs external clock, RTI⁽⁴⁾	0.8 MHz to 1.2 MHz, gain = 1 V/V			±0.05		μV/kHz
dV_OS/df	vs external clock, RTI⁽⁴⁾	0.8 MHz to 1.2 MHz, gain = 128 V/V			±0.001		μV/kHz
	Long-term stability⁽⁵⁾	Gain = 128 V/V			3.5		nV/month
	Input impedance	Single-ended and differential			> 1		GΩ
	Input capacitance, IN1 / IN2	Single-ended			12 / 8		pF
	Input voltage	Gain = 1 V/V, gain = 128 V/V, T_A = –40°C to +105°C		(VSN) + 2.5		(VSP) – 2.5	V
CMR	Common-mode rejection, RTI	Gain = 1 V/V			±0.3	±3	μV/V
		Gain = 128 V/V			±0.08	±0.8
		Gain = 128 V/V, T_A = –40°C to +105°C			±0.1	±1.5
SINGLE-ENDED OUTPUT CONNECTION
V_OS	Offset voltage, RTI, SE out	Gain = 1 V/V, 1.375 V/V, SE			±120		μV
V_OS	Offset voltage, RTI, SE out	Gain = 1V/V			±3		μV
dV_OS/dT	vs temperature, SE out	Gain = 1 V/V, SE, T_A = –40°C to +105°C			0.6		μV/°C
dV_OS/dT	vs temperature, SE out	Gain = 64 V/V, SE, T_A = –40°C to +105°C			0.05		μV/°C
INPUT BIAS CURRENT⁽⁴⁾
I_B	Bias current	Gain = 1 V/V			±0.3	±1	nA
		Gain = 128 V/V			±0.8	±2
		Gain = 1 V/V, gain = 128 V/V, T_A = –40°C to +105°C			±0.6	±2
I_OS	Offset current	Gain = 1 V/V, gain = 128 V/V			±0.1	±0.5	nA
I_OS	Offset current	Gain = 1 V/V, gain = 128 V/V, T_A = –40°C to +105°C			±0.9	±2	nA
NOISE
e_NI	Voltage noise, RTI; target	f = 0.01 Hz to 10 Hz	R_S = 0 Ω, G = 128 V/V		420		nV_PP
		f = 0.01 Hz to 10 Hz	R_S = 0 Ω, G = 1 V/V		4.5		μV_PP
		f = 1 kHz	R_S = 0 Ω, G = 128 V/V		22		nV/√Hz
		f = 1 kHz	R_S = 0 Ω, G = 1 V/V		240		nV/√Hz
I_N	Current noise, RTI	f = 0.01 Hz to 10 Hz	R_S = 10 MΩ, G = 128 V/V		1.7		pA_PP
I_N	Current noise, RTI	f = 1 kHz	R_S = 10 MΩ, G = 128 V/V		90		fA/√Hz
GAIN (Output Swing = ±4.5 V)⁽⁶⁾
	Range of input gain				⅛ to 128		V/V
	Range of output gain				1 and 1⅜		V/V
	Gain error, all binary steps	All gains			±0.03	±0.15	%
	vs temperature⁽²⁾⁽⁷⁾	No load, all gains except G = 128 V/V, T_A = –40°C to +105°C			–0.5	±2	ppm/°C
	vs temperature⁽²⁾⁽⁷⁾	No load, G = 128 V/V, T_A = –40°C to +105°C			–1	±3	ppm/°C
	Gain step matching⁽⁴⁾ (gain to gain)	No load, all gains		See
	Nonlinearity	No load, all gains⁽³⁾			1.5	10	ppm
	Nonlinearity over temperature⁽²⁾	No load, all gains, T_A = –40°C to +105°C			3		ppm
OUTPUT
	Voltage output swing from rail⁽⁴⁾	T_A = –40°C to +105°C	VSOP = 5 V, load current 2 mA		40	100	mV
	Voltage output swing from rail⁽⁴⁾	T_A = –40°C to +105°C	VSOP = 2.7 V, load current 1.5 mA			100	mV
	Capacitive load drive				500		pF
I_SC	Short-circuit current	To VSOP/2, gain = 1.375 V/V		7	15	25	mA
	Output resistance	Each output VOP and VON			200		mΩ
VOCM
	VOCM supply voltage	VSP – 2 V > VOCM, T_A = –40°C to +105°C		(VSON) + 0.1		(VSOP) – 0.1	V
I_B	Bias current into VOCM				3	100	nA
	VOCM input resistance				1		GΩ
INTERNAL OSCILLATOR
	Frequency of internal clock⁽²⁾⁽⁴⁾			0.8	1	1.2	MHz
	Ext. oscillator frequency			0.8	1	1.2	MHz
FREQUENCY RESPONSE
GBP	Gain bandwidth product⁽⁴⁾	G > 4			6		MHz
SR	Slew rate⁽⁴⁾, 4-V_PP output step	G = 1, C_L = 100 pF, BUF On			1		V/μs
		G = 8, C_L = 100 pF			2		V/μs
		G = 128, C_L = 100 pF			1		V/μs
t_S	Settling time⁽⁴⁾	To 0.01%	G = 8, V_O = 8-V_PP step		20		μs
		To 0.01%	G = 128, V_O = 8-V_PP step		40		μs
		To 0.001%	G = 8, V_O = 8-V_PP step		30		μs
		To 0.001%	G = 128, V_O = 8-V_PP step		40		μs
	Overload recovery, input⁽⁴⁾	0.5 V over supply, G = ⅛ to 128			8		μs
	Overload recovery, output⁽⁴⁾	±5.5-V_P input, G = 1 V/V			6		μs
INPUT MULTIPLEXER (Two-Channel)
	Crosstalk, INP1 to INP2	At dc, gain = 128 V/V			< –130		dB
	Series-resistance⁽⁴⁾—see Figure 44				600		Ω
	Switch on-resistance⁽⁴⁾				450		Ω
	Current source and sink⁽⁴⁾	To GND		70	95	125	μA
INPUT CURRENT BUFFER (BUF)
V_OS	Offset voltage⁽⁴⁾	Buffer active			15		mV
DIGITAL I/O (Supply: 2.7 V to 5.5 V)
	Input (logic low threshold)			0		(DVDD)x0.2	V
	Input (logic high threshold)			0.8x(DVDD)		DVDD	V
	Output (logic low)	I_OUT = 4 mA, sink				0.7	V
	Output (logic high)	I_OUT = 2 mA, source		DVDD – 0.5			V
	SCLK, frequency					10	MHz
POWER SUPPLY: Input Stage (VSN – VSP)
	Specified voltage	T_A = –40°C to +105°C		10		36	V
	Operating voltage				10 to 38		V
I_Q	Quiescent current	T_A = –40°C to +105°C	VSP		2.4	3	mA
I_Q	Quiescent current	T_A = –40°C to +105°C	VSN		2.1	3	mA
POWER SUPPLY: Output Stage (VSOP – VSON)
	Specified voltage	VSP – 1.5 V ≥ VSOP, T_A = –40°C to +105°C		2.7		5.5	V
	Voltage for VSOP, upper limit	(VSP – 2 V) > VOCM, (VSP – 5 V) > VSON			(VSP)		V
	Voltage for VSON	(VSP – 2 V) > VOCM, VSP ≥ VSOP			(VSN) to (VSP) – 5		V
I_Q	Quiescent Current	VSOP, T_A = –40°C to +105°C			0.75	1	mA
POWER SUPPLY: Digital (DVDD – DGND)
	Specified voltage	T_A = –40°C to +105°C		2.7		5.5	V
	Voltage for DVDD, upper limit				(VSP) – 1		V
	Voltage for DGND, lower limit				(VSN)		V
I_Q	Quiescent current⁽⁴⁾	Static condition, no external load, DVDD = 3 V, T_A = –40°C to +105°C			0.07	0.13	mA
TEMPERATURE
	Specified temperature			–40		105	°C
	Operating temperature			–55		140	°C
θ_JA	Thermal resistance	SSOP, High-K board, JESD51			80		°C/W

(1) RTI: Referred to input.

(2) Specified by design; not production tested.

(3) Only G = 1 is production tested.

(4) See section and typical characteristic graphs.

(5) 300-hour life test at +150°C demonstrated randomly distributed variation in the range of measurement limits.

(6) Gains smaller than ½ are measured with smaller output swing.

(7) See Figure 11 for typical gain error drift of various gain settings.