11.1 Layout Guidelines

Refer to Figure 33 and use the following guidelines for proper layout design:

• Connect low-ESR, 0.1-μF ceramic bypass capacitors at the V_IN and V_OUT pins.
• Decouple other active devices in the system per the device specifications.
• Use a solid ground plane to help distribute heat and reduce electromagnetic-interference (EMI) noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
• Minimize trace length between the reference and bias connections to the end device to reduce noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

Figure 33. REF50xxA-Q1 Layout Example