4.1 Absolute Maximum Ratings(1)(2)
|
MIN |
MAX |
UNIT |
Voltage applied at VCC referenced to VSS (VAMR) |
-0.3 |
4.1 |
V |
Voltage applied at VANT referenced to VSS (VAMR) |
-0.3 |
4.1 |
V |
Voltage applied to any pin (references to VSS) |
-0.3 |
VCC + 0.3 |
V |
Diode current at any device pin |
|
±2 |
mA |
(1) Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS.
(3) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
4.8 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER |
VALUE |
UNIT |
θJA |
Junction-to-ambient thermal resistance, still air(1) |
TSSOP-14 (PW) |
116.0 |
°C/W |
θJC(TOP) |
Junction-to-case (top) thermal resistance(2) |
45.1 |
°C/W |
θJB |
Junction-to-board thermal resistance(3) |
57.6 |
°C/W |
ΨJB |
Junction-to-board thermal characterization parameter |
57.0 |
°C/W |
ΨJT |
Junction-to-top thermal characterization parameter |
4.6 |
°C/W |
θJA |
Junction-to-ambient thermal resistance, still air(1) |
VQFN-16 (RGT) |
48.8 |
°C/W |
θJC(TOP) |
Junction-to-case (top) thermal resistance(2) |
60.8 |
°C/W |
θJB |
Junction-to-board thermal resistance(3) |
21.9 |
°C/W |
ΨJB |
Junction-to-board thermal characterization parameter |
21.9 |
°C/W |
ΨJT |
Junction-to-top thermal characterization parameter |
1.5 |
°C/W |
θJC(BOT) |
Junction-to-case (bottom) thermal resistance(4) |
7.1 |
°C/W |
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
4.9 Serial Communication Protocol Timings
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER |
MIN |
TYP |
MAX |
UNIT |
tSPIvsI2C |
Time after power-up or reset until SCMS/CS is sampled for SPI or I2C decision(1) |
1 |
|
10 |
ms |
tReady |
Time after power-up or reset until device is ready to communicate using SPI or I2C(2) |
|
|
20 |
ms |
(1) The SCMS/CS pin is sampled after tSPIvsI2C(MIN) at the earliest and after tSPIvsI2C(MAX) at the latest.
(2) The device is ready to communicate after tReady(MAX) at the latest.