ZHCSE57A September   2015  – November 2015 RF430CL331H

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 典型应用
  2. 2修订历史记录
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Connections for Unused Pins
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Recommended Operating Conditions, Resonant Circuit
    5. 4.5 Supply Currents
    6. 4.6 Electrical Characteristics, Digital Inputs
    7. 4.7 Electrical Characteristics, Digital Outputs
    8. 4.8 Thermal Characteristics
    9. 4.9 Timing and Switching Characteristics
      1. 4.9.1 Reset Timing
      2. 4.9.2 Serial Communication Protocol Timing
      3. 4.9.3 RF143B NFC/RFID Analog Front End
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Terms and Acronyms
    4. 5.4  Serial Communication Interface
    5. 5.5  Communication Protocol
    6. 5.6  I2C Protocol
      1. 5.6.1 I2C Examples
        1. 5.6.1.1 I2C Write
        2. 5.6.1.2 I2C Read
      2. 5.6.2 BIP-8 Communication Mode With I2C
    7. 5.7  NFC Type 4B Tag Platform
      1. 5.7.1 ISO/IEC 14443-3 Commands
      2. 5.7.2 NFC Tag Type 4 Commands
      3. 5.7.3 Data Rate Settings
    8. 5.8  NDEF Structure
    9. 5.9  Typical Operation
      1. 5.9.1 NDEF or Capability Container Select Procedure
      2. 5.9.2 NDEF or Capability Container Read Binary Procedure
        1. 5.9.2.1 NDEF Read Command Internal Buffer Handling
        2. 5.9.2.2 NDEF Read Command Internal Buffer Handling (With Caching)
      3. 5.9.3 NDEF or Capability Container Read Procedure (Prefetch Feature)
        1. 5.9.3.1 NDEF Read Command With Prefetch Internal Buffer Handling
      4. 5.9.4 NDEF or Capability Container Write Procedure (Blocking)
        1. 5.9.4.1 NDEF Write Command (Blocking) Internal Buffer Handling
      5. 5.9.5 NDEF or Capability Container Write Procedure (Nonblocking)
        1. 5.9.5.1 NDEF Write Procedure (Nonblocking) Internal Buffer Handling
    10. 5.10 RF Command Response Timing Limits
    11. 5.11 Registers
      1. 5.11.1  General Control Register
      2. 5.11.2  Status Register
      3. 5.11.3  Interrupt Registers
      4. 5.11.4  CRC Registers
      5. 5.11.5  Communication Watchdog Register
      6. 5.11.6  Version Register
      7. 5.11.7  NDEF File Identifier Register
      8. 5.11.8  Host Response Register
      9. 5.11.9  NDEF Block Length Register
      10. 5.11.10 NDEF File Offset Register
      11. 5.11.11 Buffer Start Register
      12. 5.11.12 SWTX Register
      13. 5.11.13 Custom Status Word Response Register
    12. 5.12 Identification
      1. 5.12.1 Revision Identification
      2. 5.12.2 Device Identification
      3. 5.12.3 JTAG Identification
      4. 5.12.4 Software Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Diagram
    2. 6.2 References
  7. 7器件和文档支持
    1. 7.1 器件支持
      1. 7.1.1 开发支持
        1. 7.1.1.1 入门和下一步
      2. 7.1.2 器件和开发工具命名规则
    2. 7.2 文档支持
      1. 7.2.1 相关文档　
    3. 7.3 社区资源
    4. 7.4 商标
    5. 7.5 静电放电警告
    6. 7.6 出口管制提示
    7. 7.7 Glossary
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Specifications

4.1 Absolute Maximum Ratings (1) (2)

MIN MAX UNIT
Voltage applied at VCC referenced to VSS (VAMR) –0.3 4.1 V
Voltage applied at VANT referenced to VSS (VAMR) –0.3 4.1 V
Voltage applied to any pin (references to VSS) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature, Tstg (3) –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS.
(3) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage During program execution no RF field present 3.0 3.3 3.6 V
During program execution with RF field present 2.0 3.3 3.6
VSS Supply voltage (GND reference) 0 V
TA Operating free-air temperature –40 85 °C
C1 Decoupling capacitor on VCC (1) 0.1 µF
C2 Decoupling capacitor on VCC (1) 1 µF
CVCORE Capacitor on VCORE (1) 0.1 0.47 1 µF
(1) Low ESR (equivalent series resistance) capacitor

4.4 Recommended Operating Conditions, Resonant Circuit

MIN NOM MAX UNIT
fc Carrier frequency 13.56 MHz
VANT_peak Antenna input voltage 3.6 V
Z Impedance of LC circuit 6.5 15.5 kΩ
LRES Coil inductance(2) 2.66 µH
CRES Total resonance capacitance(2), CRES = CIN + CTune 51.8 pF
CTune External resonance capacitance CRES – CIN (1) pF
QT Tank quality factor 30
(1) For CIN refer to Section 4.9.3.
(2) The coil inductance of the antenna LRES with the external capacitance CTune plus the device internal capacitance CIN is a resonant circuit. The resonant frequency of this LC circuit must be close to the carrier frequency fc:
fRES = 1 / [2π(LRESCRES)1/2] = 1 / [2π(LRES(CIN+CTune))1/2] ≈ fc

4.5 Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ICC(I2C) I2C, 400 kHz, Writing into NDEF memory 3.3 V 250 µA
ICC(RF enabled) RF enabled, no RF field present 3.3 V 40 µA
ICC(Inactive) Standby enable = 0, RF disabled, no serial communication 3.3 V 15 µA
ICC(Standby) Standby enable = 1, RF disabled, no serial communication 3.3 V 10 45 µA
ΔICC(StrongRF) Additional current consumption with strong RF field present 3.0 V to 3.6 V 160 µA
ICC(RF,lowVCC) Current drawn from VCC < 3.0 V with RF field present (passive operation) 2.0 V to 3.0 V 0 µA

4.6 Electrical Characteristics, Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIL Low-level input voltage 0.3 × VCC V
VIH High-level input voltage 0.7 × VCC V
VHYS Input hysteresis 0.1 × VCC V
IL High-impedance leakage current 3.3 V –50 50 nA
RPU(RST) Integrated RST pullup resistor 20 35 50 kΩ

4.7 Electrical Characteristics, Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOL Output low voltage IOL = 3 mA 3 V 0.4 V
3.3 V 0.4
3.6 V 0.4
VOH Output high voltage IOH = –3 mA 3 V 2.6 V
3.3 V 2.9
3.6 V 3.2

4.8 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER VALUE UNIT
RθJA Junction-to-ambient thermal resistance, still air(1) TSSOP-14 (PW) 116.0 °C/W
RθJC(TOP) Junction-to-case (top) thermal resistance(2) 45.1 °C/W
RθJB Junction-to-board thermal resistance(3) 57.6 °C/W
ΨJB Junction-to-board thermal characterization parameter 57.0 °C/W
ΨJT Junction-to-top thermal characterization parameter 4.6 °C/W
RθJA Junction-to-ambient thermal resistance, still air(1) VQFN-16 (RGT) 48.8 °C/W
RθJC(TOP) Junction-to-case (top) thermal resistance(2) 60.8 °C/W
RθJC(BOT) Junction-to-case (bottom) thermal resistance(4) 7.1 °C/W
RθJB Junction-to-board thermal resistance(3) 21.9 °C/W
ΨJB Junction-to-board thermal characterization parameter 21.9 °C/W
ΨJT Junction-to-top thermal characterization parameter 1.5 °C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

4.9 Timing and Switching Characteristics

4.9.1 Reset Timing

Table 4-1 I2C Power-up Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN MAX UNIT
tReady Time after power up or reset until device is ready to communicate using I2C(1) 20 ms
(1) The device is ready to communicate after tReady(MAX) at the latest.

4.9.2 Serial Communication Protocol Timing

Table 4-2 I2C Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fSCL SCL clock frequency (with Master supporting clock stretching according to I2C standard, or when the device is not being addressed) 3.3 V 0 400 kHz
SCL clock frequency (device being addressed by Master not supporting clock stretching) Write 3.3 V 0 120
Read 3.3 V 0 100
tHD,STA Hold time (repeated) START fSCL ≤ 100 kHz 3.3 V 4 µs
fSCL > 100 kHz 0.6
tSU,STA Setup time for a repeated START fSCL ≤ 100 kHz 3.3 V 4.7 µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 3.3 V 0 ns
tSU,DAT Data setup time 3.3 V 250 ns
tSU,STO Setup time for STOP 3.3 V 4 µs
tSP Pulse duration of spikes suppressed by input filter 3.3 V 6.25 75 ns
RF430CL331H i2c_timing_slas850.gif Figure 4-1 I2C Mode Timing

4.9.3 RF143B NFC/RFID Analog Front End

Table 4-3 Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDDH Antenna rectified voltage Peak voltage limited by antenna limiter 3.0 3.3 3.6 V
IDDH Antenna load current RMS, without limiter current 100 µA
CIN Input capacitance ANT1 to ANT2, 2 V RMS 31.5 35 38.5 pF

Table 4-4 ISO/IEC 14443B ASK Demodulator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
DR10 Input signal data rate 10% downlink modulation, 7% to 30% ASK, ISO1443B 106 848 kbps
m10 Modulation depth 10%, tested as defined in ISO/IEC 10373-6 7% 30%

Table 4-5 ISO/IEC 14443B-Compliant Load Modulator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
fPICC Uplink subcarrier modulation frequency 0.2 1 MHz
VA_MOD Modulated antenna voltage, VA_unmod = 2.3 V 0.5 V
VSUB14 Uplink modulation subcarrier level, ISO/IEC 14443B: H = 1.5 to 7.5 A/m 22/H0.5 mV

Table 4-6 Power Supply

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLIM Limiter clamping voltage ILIM ≤ 70 mA RMS, f = 13.56 MHz 3.0 3.6 Vpk
ILIM,MAX Maximum limiter current 70 mA
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