9.2.1 Signal Groups Description

Figure 50. CPU (DSP Core) Signals

Figure 51. Peripheral Signals

Figure 52. Peripheral Signals (continued)

9.2.2 CPU (DSP Core) Description

The CPU fetches VelociTI advanced VLIW (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Functional Block Diagram and Figure 53). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. Register access using the register file across the CPU supports one read and one write per cycle.

Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most instructions can access any of the 32 registers. However, some registers are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically true). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are linked together by 1 bits in the least significant bit (LSB) position of the instructions. The instructions that are chained together for simultaneous execution (up to eight in total) compose an execute packet. A 0 in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the 256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

Figure 53. SMJ320C62x CPU (DSP Core) Data Paths

9.2.3 Clock PLL

Most of the internal C6203 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 54, and Table 3 through Table 17 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 55 shows the external PLL circuitry for a system with only x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the C6203 device and the external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. Observe the minimum CLKIN rise and fall times. For the input clock timing requirements, see the input and output clocks in Specifications. Table 2 lists some examples of compatible CLKIN external clock sources:

1. For the PLL options and CLKMODE pins setup, see Table 3 and Table 17.

2. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.

3. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter).

4. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

Figure 54. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

1. For a system with only PLL x1 (bypass) mode, short the PLLF to PLLG.

2. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

Figure 55. External PLL Circuitry for x1 (Bypass) PLL Mode Only

9.3.1 Memory Map Summary

Table 4 shows the memory map address ranges of the C6203 device. The C6203 device has the capability of a MAP 0 or MAP 1 memory block configuration. These memory block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For the C6203 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For more detailed information on the C6203 device settings, which include the device boot mode configuration at reset and other device-specific configurations, see the TMS320C6000 Peripherals Reference Guide (SPRU190) for information regarding boot configuration.

9.3.2 Peripheral Register Descriptions

Table 5 through Table 14 identify the peripheral registers for the C6203 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the TMS320C6000 Peripherals Reference Guide (SPRU190).

The C6203 DMA supports up to four independent programmable DMA channels, plus an auxiliary channel used for servicing the HPI module. The four main DMA channels can be read/write synchronized based on the events shown in Table 15. Selection of these events is done by the RSYNC and WSYNC fields in the Primary Control registers of the specific DMA channel. For more detailed information on the DMA module, associated channels, and event-synchronization, see the TMS320C6000 Peripherals Reference Guide (SPRU190).

9.3.3 Interrupt Sources and Interrupt Selector

The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 16. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00 to INT_03) are non-maskable and fixed. The remaining interrupts (INT_04 to INT_15) are maskable and default to the interrupt source specified in Table 16. The interrupt source for interrupts 4 to 15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).