SGUS033A February   2002  – May 2016 SMJ320C6203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Characteristics of the C6203 DSP
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Timing Requirements for CLKIN (PLL Used)
    6. 7.6  Timing Requirements for CLKIN [PLL Bypassed (x1)]
    7. 7.7  Timing Requirements for XCLKIN
    8. 7.8  Timing Requirements for Asynchronous Memory Cycles
    9. 7.9  Timing Requirements for Synchronous-Burst SRAM Cycles
    10. 7.10 Timing Requirements for Synchronous DRAM Cycles
    11. 7.11 Timing Requirements for the HOLD/HOLDA Cycles
    12. 7.12 Timing Requirements for Reset
    13. 7.13 Timing Requirements for Interrupt Response Cycles
    14. 7.14 Timing Requirements for Synchronous FIFO Interface
    15. 7.15 Timing Requirements for Asynchronous Peripheral Cycles
    16. 7.16 Timing Requirements With External Device as Bus Master
    17. 7.17 Timing Requirements With C62x as Bus Master
    18. 7.18 Timing Requirements With External Device as Asynchronous Bus Master
    19. 7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)
    20. 7.20 Timing Requirements for McBSP
    21. 7.21 Timing Requirements for FSR when GSYNC = 1
    22. 7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
    23. 7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    24. 7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    25. 7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    26. 7.26 Timing Requirements for Timer Inputs
    27. 7.27 Timing Requirements for JTAG Test Port
    28. 7.28 Switching Characteristics for CLKOUT2
    29. 7.29 Switching Characteristics for XFCLK
    30. 7.30 Asynchronous Memory Timing Switching Characteristics
    31. 7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles
    32. 7.32 Switching Characteristics for Synchronous DRAM Cycles
    33. 7.33 Switching Characteristics for the HOLD/HOLDA Cycles
    34. 7.34 Switching Characteristics for Reset
    35. 7.35 Switching Characteristics for Interrupt Response Cycles
    36. 7.36 Switching Characteristics for Synchronous FIFO Interface
    37. 7.37 Switching Characteristics for Asynchronous Peripheral Cycles
    38. 7.38 Switching Characteristics With External Device as Bus Master
    39. 7.39 Switching Characteristics With C62x as Bus Master
    40. 7.40 Switching Characteristics With External Device as Asynchronous Bus Master
    41. 7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)
    42. 7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)
    43. 7.43 Switching Characteristics for McBSP
    44. 7.44 Switching Characteristics for McBSP as SPI Master or Slave
    45. 7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    46. 7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    47. 7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    48. 7.48 Switching Characteristics for DMAC Outputs
    49. 7.49 Switching Characteristics for Timer Outputs
    50. 7.50 Switching Characteristics for Power-Down Outputs
    51. 7.51 Switching Characteristics for JTAG Test Port
  8. 8 Parameter Measurement Information
    1. 8.1 Signal Transition Levels
    2. 8.2 Timing Parameters and Board Routing Analysis
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Signal Groups Description
      2. 9.2.2 CPU (DSP Core) Description
      3. 9.2.3 Clock PLL
    3. 9.3 Register Maps
      1. 9.3.1 Memory Map Summary
      2. 9.3.2 Peripheral Register Descriptions
      3. 9.3.3 Interrupt Sources and Interrupt Selector
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 System-Level Design Considerations
    3. 11.3 Power-Supply Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Software Development Tools
        2. 12.1.2.2 Hardware Development Tools
      3. 12.1.3 Device and Development-Support Tool Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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散热焊盘机械数据 (封装 | 引脚)
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11 Power Supply Recommendations

11.1 Power-Supply Sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.

11.2 System-Level Design Considerations

System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board.

11.3 Power-Supply Design Considerations

For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP and is corrected after the CPU detects an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns after the I/O power supply is turned on and the CPU detects a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw.

A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up. See the Using the TPS56300 to Power DSPs application report (SLVA088). A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP.

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications using the C6000 platform of DSPs, the PCB should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

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