ZHCSK05D July 2019 – October 2022 SN3257-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VDD | Power supply voltage | 1.5 | 5.5 | V | ||
IDD | Active supply current | VSEL = 0 V, 1.4 V or VDD VS = 0 V to 5.5 V | 40 | 68 | μA | |
IDD_STANDBY | Supply current when disabled | VEN = 1.4 V or VDD VS = 0 V to 5.5 V | 7.5 | 15 | µA | |
DC CHARACTERISTICS | ||||||
RON | On-resistance | VS = 0 V to VDD×2 VS(max) = 5.5 V ISD = 8 mA Refer to ON-State Resistance Figure | 2 | 5 | Ω | |
ΔRON | On-resistance match between channels | VS = VDD ISD = 8 mA Refer to ON-State Resistance Figure | 0.07 | 0.8 | Ω | |
RON (FLAT) | On-resistance flatness | VS = 0 V to VDD ISD = 8 mA Refer to ON-State Resistance Figure | 1 | 2.5 | Ω | |
IPOFF | Powered-off I/O pin leakage current | VDD = 0 V VS = 0 V to 3.6 V VD = 0 V Refer to Ipoff Leakage Figure | –8 | 0.01 | 8 | µA |
IS(OFF) ID(OFF) | OFF leakage current | Switch Off VD = 0.8×VDD / 0.2×VDD VS = 0.2×VDD / 0.8×VDD Refer to Off Leakage Figure | –900 | 0.03 | 900 | nA |
ID(ON) IS(ON) | ON leakage current | Switch On VD = 0.8×VDD / 0.2×VDD, S pins floating or VS = 0.8×VDD / 0.2×VDD, D pins floating Refer to On Leakage Figure | –900 | 0.01 | 900 | nA |
LOGIC INPUTS | ||||||
VIH | Input logic high | 1.2 | 5.5 | V | ||
VIL | Input logic low | 0 | 0.45 | V | ||
IIH | Input high leakage current | VSEL = 1.8 V, VDD | 1 | ±2 | μA | |
IIL | Input low leakage current | VSEL = 0 V | 0.2 | ±2 | μA | |
RPD | Internal pull-down resistor on logic pins | 6 | MΩ | |||
CI | Logic input capacitance | VSEL = 0 V, 1.8 V or VDD f = 1 MHz | 3 | pF |