8.1 Overview

The SNx4HC165 is an 8-bit Parallel load shift register with 1 serial input and 8 parallel load input. The device loads all the 8 bits simultaneously through parallel load input when SH/LD is low. This will also ignore any input at CLK or CLK INH.

The device shifts the data when CLK toggles. The data is shifted on rising edge of the clock. Clock Inhibit (CLK INH) inhibits the clock function resulting in no change of the output. If SH/LD is low clock inputs are ignored. To realize the shift function, SH/LD should be high.

CLK and CLK INH functions are interchangeable. If CLK is low then change a clock signal at CLK INH pin causes a shift of data to Q_H. If CLK INH is Low clock signal on CLK pin shifts the data out to Q_H.

8.2 Functional Block Diagram

Figure 3. Logic Diagram Positive Logic

Figure 4. Typical Shift, Load, and Inhibit Sequence

8.3 Feature Description

The SNx4HC165 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and Low Power Consumption, 80-μA maximum I. It is typically t_pd = 13 ns and has ±4-mA output drive at 5 V with low input current of 1-μA maximum. The device features the direct overloading load of data input, meaning parallel data is loaded irrespective of clock signals.

8.4 Device Functional Table

Table 1 lists the functional modes of the SNx4HC165.