Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-B11D1586-D1E1-4042-9D17-D5500C669E34.html#GUID-B11D1586-D1E1-4042-9D17-D5500C669E34. The worst case resistance is calculated with the maximum input voltage, given in the GUID-4854D19B-9DC3-4F29-8E22-0C3EA2F8F634.html#GUID-4854D19B-9DC3-4F29-8E22-0C3EA2F8F634, and the maximum input leakage current, given in the GUID-B11D1586-D1E1-4042-9D17-D5500C669E34.html#GUID-B11D1586-D1E1-4042-9D17-D5500C669E34, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-82E9E3E2-777C-45E2-92CF-04B6272268FA.html#GUID-82E9E3E2-777C-45E2-92CF-04B6272268FA to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.