Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the Section 5.6 and Section 5.7. The worst case resistance is calculated with the maximum input voltage, given in the Section 5.1, and the maximum input leakage current, given in the Section 5.6 and Section 5.7, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Section 5.3 and Section 5.4 to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.