ZHCSPJ9B February   2022  – December 2023 SN54SLC8T245-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 0.7 V
    7. 5.7  Switching Characteristics, VCCA = 0.8 V
    8. 5.8  Switching Characteristics, VCCA = 0.9 V
    9. 5.9  Switching Characteristics, VCCA = 1.2 V
    10. 5.10 Switching Characteristics, VCCA = 1.5 V
    11. 5.11 Switching Characteristics, VCCA = 1.8 V
    12. 5.12 Switching Characteristics, VCCA = 2.5 V
    13. 5.13 Switching Characteristics, VCCA = 3.3 V
    14. 5.14 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
      2. 7.3.2 Multiple Direction Control Pins
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.2 Multiple Direction Control Pins

Two control pins are used to configure the 8 data I/Os. I/O channels 1 through 4 are grouped together and I/O channels 5 through 8 are banked together. The benefit of this is to permit simultaneous up-translation and down-translation within one device. This eliminates the need for multiple devices, where each device can only provide up-translation or down-translation sequentially. Simultaneous up and down translation is supported when both VCCA and VCCB are at least 1.40 V.
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