11.1 Layout Guidelines

On-chip IEC ESD protection is sufficient for laboratory and portable equipment but often insufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices.

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design.

For a successful PCB design, start with the design of the protection circuit in mind.

• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use V_CC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the V_CC pins of transceiver, UART, and controller ICs on the board.
• Use at least two vias for V_CC and ground connections of bypass capacitors and protection devices to minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.
• Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to 200 mA.

11.2 Layout Example

Figure 25. SN55HVD75-EP Half-Duplex Layout Example