ZHCSND7 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

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订购信息

9.2.2.1 Pin Configuration

Here is an example of how to configure the SN6507-Q1 pins in 5 simple steps.

Step 1: Set the Switching Frequency

First, set the driver switching frequency with RCLK using Table 8-1.

For example: RCLK = 9.6 kΩ or shorted to GND, sets typical fSW at about 1 MHz.

Step 2: Set the Input UVLO

The EN/UVLO (undervoltage lockout) pins are used to set minimum input voltage that the driver starts switching. The resister divider value can be calculated by Equation 3.

For example, if the input threshold (VON) is expected to be at 9 V, the resistors are calculated as RENT/RENB = 5

Therefore,the resistors values are chosen as:

RENT = 5 kΩ, RENB = 1 kΩ

To make the device self-start at default UVLO thresold (2.8 V typical), users can skip Step 2 and directly short the EN/UVLO pin to VCC.

Step 3: Set the Current Limit and Soft-Start Time

The current limit can be set by a resistor on SS/ILIM pin according to Table 8-3. Peak currents may be very high during operation of the overcurrent protection system until the fault is cleared.

For example, to set the current limit is set at 500 mA (typical), the recommended RILIM is 50 kΩ.

Once RILIM is determined, substitue RILIM into Equation 5, the soft-time calculation is:

TSS=CSS275μA-0.650k

Taking 2 ms (typical) soft-start time as an example, the capacitor on SS/ILIM pin :CSS = 0.5 uF.

Note that both RILIM and CSS are required on SS/ILIM pin to ensure the robust operation of this device. Missing the RC connection or leaving the pin floating should be avoided.

Step 4: Set the Duty Cycle

For fixed input cases, the duty cycle feature is not needed. This step can be skipped by leaving DC pin floating, so that the device will operate at default maximum duty (48% typical). The maximum duty cycle is determined by the switching period and the deadtime (70 ns typical) to avoid overlap of two power switches.

For wide-input cases, the duty cycle feature can be enabled by connecting a resistor RDC on DC pin, and an inductor at the output side. The inductor selection is presented in Section 9.2.2.4.

To achieve maximum input compensation, the DC is set close to 0.25 (25% duty cycle) at typical VCC (24 V). The RDC is calculated as 50.9 kΩ by substituting DC = 0.25, VCC = 24 V, and RCLK = 9.6 into Equation 1, where both RCLK and RDC are in kΩ.
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