To allow optimization of EMI with respect to efficiency, the SN6507-Q1 is designed to allow a resistor (R_SR) to select the strength of the driver of PowerFETs turning on. As shown in Figure 8-7 below, the slew rate of the switching edges is controllable with the resistor. Rolling off harmonics through slew rate control can eliminate the need for shielding and common mode chokes in many applications.

The EMI benefit of slew rate control may result in slightly reduced efficiency and higher peak current (I_{SW_SR}). When the feature slows down the charging and discharging of the gate capacitance, the extended transition times of the FETs increases the transition losses during each switching cycle. This increases power dissipation, which decreases efficiency and exacerbates thermal concerns. This will limit how much the slew rate can be reduced. Another cost is the peak current of each cyle will be increased. It is because the slow edges reduce the on-time (I_{ON_SR}) and eventually the peak current (I_{SW_SR}) will increase to deliver the same average current to the load on each cycle.

The slew rate at different V_IN is programmed by R_SR. Higher R_SR values configure SN6507-Q1 for slower slew rates across V_CC levels while lower R_SR values configure SN6507-Q1 for faster slew rates. The relationship between V_CC and the slew rate for 12 V and 24 V cases are listed in Table 8-2 below. As the slew rate is independent of the switching frequency, care must be taken that at high frequencies, the slew rate should be fast enough to maximize the output power delivery to the load. If the SR pin is left floating, the slew rate will be set to the default value. An SR pin short to GND is read as a fault condition, and the device will stop switching.