SN6507-Q1 device supports soft-start feature. Upon power up or when EN/UVLO pin transitions from Low to High, the gate drive of the output powerFET is gradually increased over a period of time from 0 V to full driving strength. Soft-start prevents high inrush current from VCC while charging large secondary side decoupling capacitors, and also prevents overshoot in secondary voltage during power-up.

The sort-start time to ramp to the peak switch current is calculated by the capacitor and resistor on SS/ILIM pin with the following formula.

During soft-start, the over-current protection is disabled. To ensure a smooth transition between soft-start and the steady state, it's recommended to have a C_SS value between 50 nF and 5 µF with an output capacitor, C_OUT, of less than 10 times the value of C_SS.