Start-up and shutdown are controlled by the both EN/UVLO pin and VCC pin. For the device to remain in shutdown mode, apply a voltage below EN_UVLO to the EN/UVLO pin. In shutdown mode, the quiescent current is less than 0.8 µA (typical). If EN/UVLO pin sees a voltage higher than EN_UVLO, but V_IN is still below VCC_UVLO, the SW node is inactive. Once the V_IN is above VCC_UVLO, the chip begins to switch normally, provided the EN/UVLO voltage is above 1.5 V.

There are three ways to enable the device operation. The simplest way is to connect the EN/UVLO pin to VCC pin, allowing self-start-up of the device when VCC pin voltage is above VCC_UVLO level. However, many applications benefit from an input UVLO level different than that provided internal UVLO. So another way is to employ an enable resistor divider network as shown in Figure below, which establishes a programmable UVLO threshold. The thrid way is to connect an external logic output to drive this pin, allowing user-defined system power sequencing.

EN/UVLO pin has a 5 µs (typical) glitch filter to help avoid false turn-on and turn-off due to noise coupling. It also comes with an internal pull down design to ensure the device is in shutdown mode when the pin is left floating.

Resistor values can be calculated using Equation below, where the input turn on threshold V_{IN_UVLO} is the desired typical start-up input voltage, EN_UVLO is 1.5 V typical, and R_ENT and R_ENB are in Ω.