ZHCSAT9I september 2012 – october 2020 SN65DSI83
PRODUCTION DATA
| DESIGN PARAMETERS | EXAMPLE VALUE |
|---|---|
| VCC | 1.8 V (±5%) |
| Clock Source (REFCLK or DSIA_CLK) | DSIA_CLK |
| REFCKL Frequency | N/A |
| DSIA Clock Frequency | 500 MHz |
| PANEL INFORMATION | |
| Pixel Clock (MHz) | 83 MHz |
| Horizontal Active (pixels) | 1280 |
| Horizontal Blanking (pixels) | 384 |
| Vertical Active (lines) | 800 |
| Vertical Blanking (lines) | 30 |
| Horizontal Sync Offset (pixels) | 64 |
| Horizontal Sync Pulse Width (pixels) | 128 |
| Vertical Sync Offset (lines) | 3 |
| Vertical Sync Pulse Width (lines) | 7 |
| PANEL INFORMATION (continued) | |
| Horizontal Sync Pulse Polarity | Negative |
| Vertical Sync Pulse Polarity | Negative |
| Color Bit Depth (6 bpc or 8 bpc) | 6-bit |
| Number of LVDS Lanes | 1 × [3 Data Lanes + 1 Clock Lane] |
| DSI INFORMATION | |
| Number of DSI Lanes | 1 × [4 Data Lanes + 1 Clock Lane] |
| DSI Clock Frequency(MHz) | 500 MHz |
| Dual DSI Configuration(Odd/Even or Left/Right) | N/A |