The video resolution parameters required by the panel need to be programmed into the SN65DSI83 device. For this example, the parameters programmed would be the following:

Horizontal Active = 1280 or 0x500

CHA_ACTIVE_LINE_LENGTH_LOW = 0x00

CHA_ACTIVE_LINE_LENGTH_HIGH = 0x05

Vertical Active = 800 or 0x320

CHA_VERTICAL_DISPLAY_SIZE_LOW = 0x20

CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x03

Horizontal Pulse Width = 128 or 0x80

CHA_HSYNC_PULSE_WIDTH_LOW = 0x80

CHA_HSYNC_PULSE_WIDTH_HIGH = 0x00

Vertical Pulse Width = 7

CHA_VSYNC_PULSE_WIDTH_LOW = 0x07

CHA_VSYNC_PULSE_WIDTH_HIGH = 0x00

Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth)

Horizontal Backporch = 384 – (64 + 128)

Horizontal Backporch = 192 or 0xC0

CHA_HORIZONTAL_BACK_PORCH = 0xC0

Vertical Backporch = VerticalBlanking – (VerticalSyncOffset +VerticalSyncPulseWidth)

Vertical Backporch = 30 – (3 + 7)

Vertical Backporch = 20 or 0x14

CHA_VERTICAL_BACK_PORCH = 0x14

Horizontal Frontporch = HorizontalSyncOffset

Horizontal Frontporch = 64 or 0x40

CHA_HORIZONTAL_FRONT_PORCH = 0x40

Vertical Frontporch = VerticalSyncOffset

Vertical Frontporch = 3

CHA_VERTICAL_FRONT_PORCH = 0x03

The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and configuring the TEST PATTERN GENERATION PURPOSE ONLY register as shown in Table 7-8.

LVDS clock is derived from the DSI channel A clock. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be set to enable the internal PLL.

LVDS_CLK_RANGE = 2 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz

HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A

DSI_CLK_DIVIDER = 00101 – Divide by 6

CHA_DSI_LANES = 00 – Four lanes are enabled

CHA_DSI_CLK_RANGE = 0x64 – 500 MHz