The SN65DSI83 device supports the MIPI defined ULPS. While the device is in the ULPS, the CSR registers are accessible via I²C interface. ULPS sequence must be issued to all active DSI CLK and, or DSI data lanes of the enabled DSI channels for the SN65DSI83 device to enter the ULPS. The following sequence must be followed to enter and exit the ULPS.

1. The host issues a ULPS entry sequence to all DSI CLK and data lanes enabled.
2. When the host is ready to exit the ULPS mode, the host issues a ULPS exit sequence to all DSI CLK and data lanes that need to be active in normal operation.
3. Wait for the PLL_LOCK bit (CSR 0x0A.7) to be set.
4. Set the SOFT_RESET bit (CSR 0x09.0).
5. Device resumes normal operation (that is, video streaming resumes on the panel).