ZHCSAT9I september 2012 – october 2020 SN65DSI83
PRODUCTION DATA
The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI® D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.