ZHCSFS1A December   2016  – June 2018 SN65DSI84-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Initialization Sequence
      3. 8.4.3 LVDS Output Formats
      4. 8.4.4 DSI Lane Merging
      5. 8.4.5 DSI Pixel Stream Packets
      6. 8.4.6 DSI Video Transmission Specifications
      7. 8.4.7 Operating Modes
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Maps
      1. 8.6.1 Control and Status Registers Overview
        1. 8.6.1.1 CSR Bit Field Definitions – ID Registers
          1. 8.6.1.1.1 Registers 0x00 – 0x08
            1. Table 5. Registers 0x00 – 0x08 Field Descriptions
        2. 8.6.1.2 CSR Bit Field Definitions – Reset and Clock Registers
          1. 8.6.1.2.1 Register 0x09
            1. Table 6. Register 0x09 Field Descriptions
          2. 8.6.1.2.2 Register 0x0A
            1. Table 7. Register 0x0A Field Descriptions
          3. 8.6.1.2.3 Register 0x0B
            1. Table 8. Register 0x0B Field Descriptions
          4. 8.6.1.2.4 Register 0x0D
            1. Table 9. Register 0x0D Field Descriptions
        3. 8.6.1.3 CSR Bit Field Definitions – DSI Registers
          1. 8.6.1.3.1 Register 0x10
            1. Table 10. Register 0x10 Field Descriptions
          2. 8.6.1.3.2 Register 0x11
            1. Table 11. Register 0x11 Field Descriptions
          3. 8.6.1.3.3 Register 0x12
            1. Table 12. Register 0x12 Field Descriptions
        4. 8.6.1.4 CSR Bit Field Definitions – LVDS Registers
          1. 8.6.1.4.1 Register 0x18
            1. Table 13. Register 0x18 Field Descriptions
          2. 8.6.1.4.2 Register 0x19
            1. Table 14. Register 0x19 Field Descriptions
          3. 8.6.1.4.3 Register 0x1A
            1. Table 15. Register 0x1A Field Descriptions
          4. 8.6.1.4.4 Register 0x1B
            1. Table 16. Register 0x1B Field Descriptions
        5. 8.6.1.5 CSR Bit Field Definitions – Video Registers
          1. 8.6.1.5.1  Register 0x20
            1. Table 17. Register 0x20 Field Descriptions
          2. 8.6.1.5.2  Register 0x21
            1. Table 18. Register 0x21 Field Descriptions
          3. 8.6.1.5.3  Register 0x24
            1. Table 19. Register 0x24 Field Descriptions
          4. 8.6.1.5.4  Register 0x25
            1. Table 20. Register 0x25 Field Descriptions
          5. 8.6.1.5.5  Register 0x28
            1. Table 21. Register 0x28 Field Descriptions
          6. 8.6.1.5.6  Register 0x29
            1. Table 22. Register 0x29 Field Descriptions
          7. 8.6.1.5.7  Register 0x2C
            1. Table 23. Register 0x2C Field Descriptions
          8. 8.6.1.5.8  Register 0x2D
            1. Table 24. Register 0x2D Field Descriptions
          9. 8.6.1.5.9  Register 0x30
            1. Table 25. Register 0x30 Field Descriptions
          10. 8.6.1.5.10 Register 0x31
            1. Table 26. Register 0x31 Field Descriptions
          11. 8.6.1.5.11 Register 0x34
            1. Table 27. Register 0x34 Field Descriptions
          12. 8.6.1.5.12 Register 0x36
            1. Table 28. Register 0x36 Field Descriptions
          13. 8.6.1.5.13 Register 0x38
            1. Table 29. Register 0x38 Field Descriptions
          14. 8.6.1.5.14 Register 0x3A
            1. Table 30. Register 0x3A Field Descriptions
          15. 8.6.1.5.15 Register 0x3C
            1. Table 31. Register 0x3C Field Descriptions
        6. 8.6.1.6 CSR Bit Field Definitions – IRQ Registers
          1. 8.6.1.6.1 Register 0xE0
            1. Table 32. Register 0xE0 Field Descriptions
          2. 8.6.1.6.2 Register 0xE1
            1. Table 33. Register 0xE1 Field Descriptions
          3. 8.6.1.6.3 Register 0xE5
            1. Table 34. Register 0xE5 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video Stop and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Example Script
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD™
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADDR 64 I/O Local I2C interface target address select. See Table 4. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI84-Q1 VCC 1.8-V power rail is connected.
A_Y0P 46 O LVDS channel A, LVDS data output 0
A_Y0N 47 O
A_Y1P 44 O LVDS channel A, LVDS data output 1
A_Y1N 45 O
A_Y2P 41 O LVDS channel A, LVDS data output 2
A_Y2N 42 O
A_Y3P 36 O LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels.
A_Y3N 37 O
A_CLKP 38 O LVDS channel A, LVDS clock output
A_CLKN 39 O
B_Y0P 61 O LVDS channel B, LVDS data output 0
B_Y0N 62 O
B_Y1P 59 O LVDS channel B, LVDS data output 1
B_Y1N 60 O
B_Y2P 56 O LVDS channel B, LVDS data output 2
B_Y2N 57 O
B_Y3P 50 O LVDS channel B, LVDS data output 3. B_Y3P and B_Y3N must be left NC for 18-bpp panels.
B_Y3N 51 O
B_CLKP 53 O LVDS channel B, LVDS clock output
B_CLKN 54 O
DA0P 19 I MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps.
DA0N 20 I
DA1P 21 I MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
DA1N 22 I
DA2P 27 I MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps.
DA2N 28 I
DA3P 29 I MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps.
DA3N 30 I
DACP 24 I MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps.
DACN 25 I
RSVD 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 — Leave unconnected
EN 2 I Chip enable and reset. The device is reset (shutdown) when the EN pin is low.
GND 23, 26, 52 G Reference ground
IRQ 33 O Interrupt signal
REFCLK 17 I This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI.
RSVD1 34 I/O Reserved. This pin must be left unconnected for normal operation.
RSVD2 1 I Reserved. This pin must be left unconnected for normal operation.
SCL 15 I Local I2C interface clock.
SDA 16 I/O Local I2C interface data
VCC 3 — 1.8-V power supply
14 —
18 —
32 —
35 —
40 —
43 —
48 —
49 —
55 —
58 —
63 —
VCORE 31 P 1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground.
PowerPAD — Reference ground
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