ZHCSAU2G September 2012 – June 2018 SN65DSI84
PRODUCTION DATA.
The SN65DSI84 DSI to FlatLink bridge features a single0channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual- Link LVDS, Single-Link LVDS interface with four data lanes per link.