ZHCSAU2G September 2012 – June 2018 SN65DSI84
PRODUCTION DATA.
The SN65DSI84 supports a pattern generation feature on LVDS Channels. This feature can be used to test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation feature is enabled.
There are three modes available for LVDS test pattern generation. The mode of test pattern generation is determined by register configuration as shown in Table 1.
| Addr. bit | Register Name |
|---|---|
| 0x20.7:0 | CHA_ACTIVE_LINE_LENGTH_LOW |
| 0x21.3:0 | CHA_ACTIVE_LINE_LENGTH_HIGH |
| 0x24.7:0 | CHA_VERTICAL_DISPLAY_SIZE_LOW |
| 0x25.3:0 | CHA_VERTICAL_DISPLAY_SIZE_HIGH |
| 0x2C.7:0 | CHA_HSYNC_PULSE_WIDTH_LOW |
| 0x2D.1:0 | CHA_HSYNC_PULSE_WIDTH_HIGH |
| 0x30.7:0 | CHA_VSYNC_PULSE_WIDTH_LOW |
| 0x31.1:0 | CHA_VSYNC_PULSE_WIDTH_HIGH |
| 0x34.7:0 | CHA_HORIZONTAL_BACK_PORCH |
| 0x36.7:0 | CHA_VERTICAL_BACK_PORCH |
| 0x38.7:0 | CHA_HORIZONTAL_FRONT_PORCH |
| 0x3A.7:0 | CHA_VERTICAL_FRONT_PORCH |