8.3.1 Reset Implementation

When the EN pin is deasserted (low), the SN65DSI85-Q1 device is in SHUTDOWN or RESET state. In this state, CMOS inputs are ignored, the MIPI D-PHY inputs are disabled and outputs are high impedance. Transitioning the EN input from a low to a high level after the V_CC supply has reached the minimum operating voltage as shown in Figure 6 is critical. This transition is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND.

Figure 6. Cold-Start V_CC Ramp Up to EN

When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference schematic for the SN65DSI85-Q1 device and, or consider an approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor.

Figure 7 and Figure 8 show both EN implementations.

Figure 7. External Capacitor Controlled EN

Figure 8. EN Input from Active Controller

When the SN65DSI85-Q1 is reset while V_CC is high, the EN pin must be held low for at least 10 ms before being asserted high as described in Table 1 to be sure that the device is properly reset. The DSI CLK lane MUST be in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted per the timing described in Table 1.