ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x10 is shown in Figure 23 and described in Table 12.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LEFT_RIGHT_PIXELS | DSI_CHANNEL_MODE | CHA_DSI_LANES | CHB_DSI_LANES | SOT_ERR_TOL_DIS | |||
| R/W-0 | R/W-01 | R/W-11 | R/W-11 | R/W-0 | |||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | LEFT_RIGHT_PIXELS | R/W | 0 | This bit selects the pixel arrangement in dual channel DSI implementations.
0: DSI channel A receives ODD pixels and channel B receives EVEN (default) 1: DSI channel A receives LEFT image pixels and channel B receives RIGHT image pixels |
| 6-5 | DSI_CHANNEL_MODE | R/W | 01 |
00: Dual-channel DSI receiver 01: Single channel DSI receiver (default) 10: Two single channel DSI receivers 11: Reserved |
| 4-3 | CHA_DSI_LANES | R/W | 11 | This field controls the number of lanes that are enabled for DSI Channel A.
Note: Unused DSI input pins on the SN65DSI85-Q1 device must be left unconnected. 00: Four lanes are enabled 01: Three lanes are enabled 10: Two lanes are enabled 11: One lane is enabled (default) |
| 2-1 | CHB_DSI_LANES | R/W | 11 | This field controls the number of lanes that are enabled for DSI Channel B.
Note: Unused DSI input pins on the SN65DSI85-Q1 must be left unconnected. 00: Four lanes are enabled 01: Three lanes are enabled 10: Two lanes are enabled 11: One lane is enabled (default) |
| 0 | SOT_ERR_TOL_DIS | R/W | 0 |
0: Single bit errors are tolerated for the start of transaction SoT leader sequence (default) 1: No SoT bit errors are tolerated |