ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0xE2 is shown in Figure 64 and described in Table 53.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHB_SYNCH_ERR_EN | CHB_CRC_ERR_EN | CHB_UNC_ECC_ERR_EN | CHB_COR_ECC_ERR_EN | CHB_LLP_ERR_EN | CHB_SOT_BIT_ERR_EN | Reserved | |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | CHB_SYNCH_ERR_EN | R/W | 0 |
0: CHB_SYNCH_ERR is masked 1: CHB_SYNCH_ERR is enabled to generate IRQ events |
| 6 | CHB_CRC_ERR_EN | R/W | 0 |
0: CHB_CRC_ERR is masked 1: CHB_CRC_ERR is enabled to generate IRQ events |
| 5 | CHB_UNC_ECC_ERR_EN | R/W | 0 |
0: CHB_UNC_ECC_ERR is masked 1: CHB_UNC_ECC_ERR is enabled to generate IRQ events |
| 4 | CHB_COR_ECC_ERR_EN | R/W | 0 |
0: CHB_COR_ECC_ERR is masked 1: CHB_COR_ECC_ERR is enabled to generate IRQ events |
| 3 | CHB_LLP_ERR_EN | R/W | 0 |
0: CHB_LLP_ERR is masked 1: CHB_ LLP_ERR is enabled to generate IRQ events |
| 2 | CHB_SOT_BIT_ERR_EN | R/W | 0 |
0: CHB_SOT_BIT_ERR is masked 1: CHB_SOT_BIT_ERR is enabled to generate IRQ events |
| 1-0 | Reserved | Reserved |