米6体育平台手机版

ZHCSDD1A July 2014 – December 2015 SN65DSI86-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PAP|64
- MPQF071C

散热焊盘机械数据 (封装 | 引脚)

PAP|64
- PPTD318A

订购信息

11 Layout

11.1 Layout Guidelines

To minimize the power supply noise floor, provide good decoupling near the SN65DSIx6 power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.1 μF) provides good performance. At the very least, TI recommends to install one 0.1-μF and one 0.01-μF capacitors near the SN65DSIx6. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSIx6 on the bottom of the PCB is often a good choice.
Note: The power supplies V_PLL, V_CCIO, V_CCA, and V_CC can be applied simultaneously.

11.1.1 DSI Guidelines

DA*P/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (±15%).
Keep away from other high speed signals.
Keep lengths to within 5 mils of each other.
Length matching should be near the location of mismatch. See Figure 4 for an example.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI.
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. TI recommends to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
The maximum trace length over FR4 between SN65DSI86 and the GPU is 25 to 30 cm.

11.1.2 eDP Guidelines

ML*P/N pairs should be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (± 15%).
Keep away from other high speed signals.
Keep lengths to within 5 mils of each other.
Length matching should be near the location of mismatch. See Figure 4 for an example.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. TI recommends to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
The maximum trace length over FR4 between SN65DSIx6 and the eDP receptacle is 4 inches for data rates less than or equal to HBR (2.7 Gbps) and 2 inches for HBR2 (5.4 Gbps).

11.1.3 Ground

TI recommends that only one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the SN65DSIx6 should be connected to this plane with vias.

11.2 Layout Example