ZHCSBP5C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
| Min number of DSI Lanes = StreamBitRate / MaxDSIClock | ||
| Min number of DSI Lanes = 3564 MBps / (500 × 2) | ||
| Min number of DSI Lanes = 3.564 lanes | ||
| Min number of DSI Lanes = 4 lanes |
After determining the number of required DSI lanes, the next step is to determine the minimum required DSI clock frequency to support the stream bit rate of the eDP panel. For 24 bpp, the calculation for determining the DSI clock frequency is as follows:
| Min Required DSI Clock Frequency = StreamBitRate / (Min_Number_DSI_Lanes × 2) | ||
| Min Required DSI Clock Frequency = 3564 / (4 × 2) | ||
| Min Required DSI Clock Frequency = 445.5 MHz |
In this example, the clock source for the SN65DSI86 is the REFCLK pin. When using the REFCLK as the clock source, any DSI Clock frequency is supported. But if the clock source was instead the DSI A clock, then the required DSI Clock frequency would need to change to a frequency supported by the SN65DSI86. When operating in this mode, any one of the following DSI A clock frequencies can be used: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz. In most cases, a eDP panel would support some variation from the ideal pixel clock frequency. For this example either 416 MHz or 460.8 MHz could be tried.
| The DSI mode, number of lanes, and DSI Clock frequency needs to be programmed into the SN65DSI86. | ||
| DSI_CHANNEL_MODE = 1 (Single DSI Channel) | ||
| CHA_DSI_LANES = 3 (for 4 lanes) | ||
| CHA_DSI_CLK_RANGE = 0x59 (equates to 445 MHz) | ||
| REFCLK_FREQ = 0x06 (27 MHz) |