The APU or GPU must provide a stream bit rate as required by the eDP panel. In this particular example, the eDP panel stream rate is 3.564 Gbps. Because the SN65DSI86 can support a DSI clock rate of up to 750 MHz (or 1.5 Gbps), the minimum number of required DSI lanes to meet the stream bit rate is three lanes. But in this example, the APU/GPU maximum DSI Clock frequency is 500 MHz. This means the number of required DSI lanes will need to be increased to four lanes.