When EN is deasserted, CMOS inputs are ignored, the MIPI D-PHY inputs are disabled, and outputs are high impedance. It is critical to transition the EN input from a low to a high level after the V_CC supply has reached the minimum recommended operating voltage. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND. To insure that the SN65DSI86 is properly reset, the EN pin must be deasserted for at least 100 µs before being asserted.

When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference schematic for the SN65DSI86 device and/or consider approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor.

Both EN implementations are shown in Figure 8-1 and Figure 8-2.

Figure 8-1 External Capacitor Controlled EN

Figure 8-2 EN Input from Active Controller