ZHCSBP5C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
The SN65DSI86 has four physical DisplayPort lanes and each physical lane can be assigned to one specific logical lane. By default, physical lanes 0 through 3 are mapped to logical lanes 0 through 3. When routing between the SN65DSI86 and a non-standard eDP receptacle, the physical to logical lane mapping can be changed so that PCB routing complexity is minimized. Table 8-12 depicts the supported logical to physical combinations based on the number of lanes programmed into the DP_NUM_LANES registers.
| DP_NUM_LANES | LN0_ASSIGN | LN1_ASSIGN | LN2_ASSIGN | LN3_ASSIGN |
|---|---|---|---|---|
| 1 | 0 or 1. 0 is recommended. | |||
| 2 | 0 or 1 | 0 or 1 | ||
| 4 | 0, 1, 2, or 3 | 0, 1, 2, or 3 | 0, 1, 2, or 3 | 0, 1, 2, or 3 |
The SN65DSI86 DisplayPort logic uses clocks from physical lane 0, and therefore these clocks from physical lane 0 will be active whenever the DP PLL is enabled. When using less than four DP lanes, the optimal power consumption is achieved by always using physical lane 0.