ZHCSBP5C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
| STEP NUMBER | DESCRIPTION | |
|---|---|---|
| 1 | EN deasserted (LOW) and all Power Supplies active and stable. Depending on whether DPPLL_CLK_SRC is REFCLK pin or the DACP/N pins, GPIO[3:1] set to value that matches the REFCLK or DACP/N frequency. See the Table 8-1 for GPIO to REFCLK/DACP/N frequency combinations. If GPIO are not going to be used to select the REFCLK/DACP/N frequency, then software must program the REFCLK_FREQ register via I2C after the EN is asserted. This knowledge of the REFCLK_FREQ is also used by the DSIx6 to determine the DSI Clock frequency when DPPLL_CLK_SRC is REFCLK pin. | |
| 2 | EN is asserted (HIGH). | |
| 3 | Configure number of DSI channels and lanes per channel. The DSIx6 defaults to 1 lane of DSI Channel A. DSI Channel B is disabled by default. When using DSI to configure the DSIx6, software needs to keep in mind the default configuration of the DSI channels only allows access to internal CSR through either 1 lane of HSDT or LPDT. Once CFR defaults are changed, all future CFR accesses should use the new DSI configuration. DSI Channel B can never be used to access internal DSIx6 CSR space. I2C access to internal DSIx6 CSR is always available. | |
| 4 | Configure REFCLK or DACP/N Frequency. If GPIO[3:1] is used to set the REFCLK or DACP/N frequency, then this step can be skipped. This step must be completed before any DisplayPort AUX channel communication can occur. SW needs to program REFCLK_FREQ to match the frequency of the clock provided to REFCLK pin or DACP/N pins. The knowledge of the REFCLK_FREQ is also used by the DSIx6 to determine the DSI Clock frequency when DPPLL_CLK_SRC is REFCLK pin. | |
| 5 | The SN65DSI86 supports polarity inversion of each of the MLP[3:0] and MLN[3:0] pins. This feature helps prevent any DisplayPort Main Link differential pair crossing on the PCB. If the system implementer uses this feature, then the MLx_POLR registers need to be updated to match the system implementation. | |
| 6 | The SN65DSI86 supports the ability to assign physical MLP/N[3:0] pins to a specific logical lane in order to help in the routing on the PCB. By default, physical pins MLP/N0 is logical lane 0, physical pins MLP/N1 is logical lane 1, physical pins MLP/N2 is logical lane 2, and physical pins MLP/N3 is logical lane 3. If the actual system implementation does not match the DSIx6 default values, then the LNx_ASSIGN fields need to be updated to match the system implementation. | |
| 7 | By default, all interrupt sources are disabled (IRQ will not get asserted). SW needs to enable interrupt sources it cares about. | |
| 8 | In an eDP application, HPD is not required. If HPD is not used, software needs to disable HPD by writing to the HPD_DISABLE register and then go to the next step. If HPD is used, then software must remain in this step until an HPD_INSERTION occurs. Once a HPD_INSERTION occurs, software can go to the next step. | |
| 9 | Resolution capability of eDP Panel through reading EDID. In a eDP application, the Panel resolution capability may be known in advance. If this is the case, then this step can be skipped. Two methods are available for reading the EDID: direct method and indirect method. | |
| 1. | Using the direct method, SW needs to program I2C_ADDR_CLAIMx registers and enable them. Once this is done, any I2C transaction that targets the I2C_ADDR_CLAIMx address will be translated into a I2C-Over-AUX transaction. In order to use the direct method, the I2C master must support clock stretching. | |
| 2. | Using the indirect method, SW needs to use Native and I2C-Over-Aux registers. When using the indirect method, the maximum read size allowed is 16 bytes. This means reading the EDID must be broken into 16-byte chunks. | |
| 10 | eDP Panel DisplayPort Configuration Data (DPCD). In eDP applications, the eDP panel DPCD information maybe known in advance. If this is the case, then this step can be skipped. SW can obtain the DPCD information by using the Native Aux Registers. The eDP panel capability is located at DisplayPort Address 0x00000 through 0x0008F. When reading the DPCD capability, SW needs to be aware that Native Aux transactions, like I2C-Over-Aux, is limited to a read size of 16 bytes. This means SW must read the DPCD in 16-byte chunks. | |
| 11 | Based on resolution and capabilities of eDP sink obtained from EDID and DPCD, GPU should program the appropriate number of data lanes (DP_NUM_LANES) and data rate (DP_DATARATE) to match source capabilities and sink requirements. SSC_ENABLE can also be set if the eDP sink supports SSC. | |
| 12 | Enable the DisplayPort PLL by writing a 1 to the DP_PLL_EN register. Before proceeding to next step, software should verify the PLL is locked by reading the DP_PLL_LOCK bit. | |
| 13 | The SN65DSI86 only supports ASSR Display Authentication method and this method is enabled by default. An eDP panel must support this Authentication method. Software will need to enable this method in the eDP panel at DisplayPort address 0x0010A. | |
| 14 | Train the DisplayPort Link. Based on the resolution requirements of the application and the capabilities of the eDP panel, software needs to choose the optimum lane count and datarate for DisplayPort Main Links. The DSIx6 provides three methods for Link Training: Manual, Fast, and Semi-Auto. | |
| 1. | Manual Method is completely under SW control. SW can follow training steps outlined in the DisplayPort Standard or SW can perform a subset of what the DisplayPort standard requires. | |
| 2. | Fast Link Train. Prior knowledge of the calibrated settings is required in order to use Fast Link Train. SW needs to program both the DSIx6 and the eDP panel with the calibrated settings. Once this is done, software can change the ML_TX_MODE from Main Link Off to Fast Link Training. The DSIx6 will transmit the enabled TPS1 and/or TPS2 pattern and then transition the ML_TX_MODE to Normal Mode. | |
| 3. | Semi-Auto Link Training. This method is intended if there is a preferred datarate and lane count but the other parameters like TX_SWING and Pre-Emphasis are not known or eDP sink does not support Fast Training. SW can transition the ML_TX_MODE to Semi-Auto Link Training. If training is successful, the LT_PASS flag will get set and the ML_TX_MODE will be transitioned to Normal Mode. If training is unsuccessful, the LT_FAIL flag will get set and the ML_TX_MODE will transition to Main Link Off. SW then will have to specify a different data rate and/or lane count combination and attempt Auto-Link training again. This is repeated until successful link training occurs. Please keep in mind that changes in data rate will cause the DP PLL to lose lock. SW should always wait until DP_PLL_LOCK bit is set before attempting another Semi-Auto Link training. | |
| 15 | Video Registers need to be programmed. Video Registers are used by the DSIx6 to recreate the video timing provided from the DSI interface to the DisplayPort interface. | |
| 16 | Configure GPIO control registers if default state if not used. The GPIO default to Inputs. | |
| 18 | Video stream can be enabled in the GPU and sent via the DSI interface to the SN65DSI86. | |
| 19 | SW can now enable the SN65DSI86 to pass the video stream provided on the DSI interface to the DisplayPort interface by writing a 1 to the VSTREAM_ENABLE register. | |