The Indirect Method is intended to be used by a GPU which does NOT support the Direct Method (Clock Stretching). The Indirect Method involves programming the appropriate CFR registers. The Indirect Method is very similar to the Native Aux method described above.

Example of Indirect I²C Read of the EDID.

1. Program the AUX_CMD = 0x4, AUX_ADDR[7:0] = 0x50, and AUX_LENGTH = 0x00.
2. Set the SEND bit.
3. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
4. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 5.
5. Program the AUX_CMD = 0x4, AUX_ADD[7:0] = 0x50, AUX_LENGTH = 0x01, and AUX_WDATA0 = 0x00.
6. Set the SEND bit.
7. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
8. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 9.
9. Program the AUX_CMD = 0x5, AUX_ADDR[7:0] = 0x50, and AUX_LENGTH = 0x00.
10. Set the SEND bit.
11. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
12. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 13.
13. Program the AUX_CMD = 0x5, AUX_ADDR[7:0] = 0x50, and AUX_LENGTH = 0x10.
14. Set the SEND bit.
15. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
16. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag, read data from AUX_RDATA0 through AUX_DATA15, and go to step 13.
17. If read of EDID is complete, the go to step 18. If read of EDID is not complete, then go to Step 13.
18. Program the AUX_CMD = 0x1, AUX_ADDR[7:0] = 0x50, and AUX_LENGTH = 0x00.
19. Set the SEND bit.
20. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
21. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 22.
22. Read of EDID finished.

Example of an indirect I²C Write (Changing EDID Segment Pointer):

1. Program the AUX_CMD = 0x4, AUX_ADDR[7:0] = 0x30, and AUX_LENGTH = 0x00.
2. Set the SEND bit.
3. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
4. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 5.
5. Program the AUX_CMD = 0x4, AUX_ADDR[7:0] = 0x30, AUX_LENGTH = 0x01, and AUX_WDATA0 = 0x01.
6. Set the SEND bit.
7. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
8. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 9.
9. Program the AUX_CMD = 0x0, AUX_ADDR[7:0] = 0x30, and AUX_LENGTH = 0x00.
10. Set the SEND bit.
11. The SN65DSI86 will clear the SEND bit once the Request has been ACKed.
12. If SEND_INT_EN is enabled and IRQ_EN is enabled, an IRQ will be asserted. GPU should make sure no error flags are set. If no error flags are set, GPU should clear the SEND_INT flag and go to step 13.
13. Finished.

The SN65DSI86 will handle all aspects of completing a request I2C-Over-Aux Read or Write. Once the requested Read or Write completes, the SN65DSI86 will clear the SEND bit and if an error occurred, the SN65DSI86 will set the NAT_I2C_FAILED flag. The NAT_I2C_FAILED flag will get set if for some reason the slave NACK the I²C Address. If the Slave NACK without completing the entire request AUX_LENGTH, the SN65DSI86 will set the AUX_SHORT flag and update the AUX_LENGTH register with the amount of data completed and then clear the SEND bit. Upon clearing the SEND bit and if IRQ assertion is enabled, the SN65DSI86 will assert IRQ.