ZHCSBP5C september 2013 – october 2020 SN65DSI86
PRODUCTION DATA
For this design example, use the parameters listed in Table 9-1.
| DESIGN PARAMETER | EXAMPLE VALUE | |||
|---|---|---|---|---|
| VCC and VCCA Supply | 1.2 V (± 5%) | |||
| VCCIO Supply | 1.8 V (± 10%) | |||
| VPLL Supply | 1.8 V (± 10%) | |||
| Clock Source (REFCLK or DSIA_CLK) | REFCLK | |||
| REFCLK Frequency (12 MHz, 19.2 MHz, 26 MHz, 27 MHz, or 38.4 MHz) | 27 MHz | |||
| DSIA Clock Frequency | N/A | |||
| eDP PANEL EDID RESOLUTION INFORMATION | ||||
| Pixel Clock (MHz) | 148.5 | |||
| Horizontal Active (pixels) | 1920 | |||
| Horizontal Blanking (pixels) | 280 | |||
| Vertical Active (lines) | 1080 | |||
| Vertical Blanking (lines) | 45 | |||
| Horizontal Sync Offset (pixels) | 88 | |||
| Horizontal Sync Pulse Width (pixels) | 44 | |||
| Vertical Sync Offset (lines) | 4 | |||
| Vertical Sync Pulse Width (lines) | 5 | |||
| Horizontal Sync Pulse Polarity | Positive | |||
| Vertical Sync Pulse Polarity | Positive | |||
| Color Bit Depth (6 bpc or 8 bpc) | 8 (24 bpp) | |||
| eDP PANEL DPCD INFORMATION | ||||
| eDP Version (1.0, 1.1, 1.2, 1.3, or 1.4) | 1.3 | |||
| Number of eDP lanes (1, 2, or 4) | 2 | |||
| Datarate Supported (1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.70 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.40 Gbps) | 2.70 | |||
| DSI INFORMATION | ||||
| APU or GPU Maximum number of DSI Lanes (1 through 8) | 4 | |||
| APU or GPU Maximum DSI Clock Frequency (MHz) | 500 | |||
| Single or Dual DSI | Single | |||
| Dual DSI Configuration (Odd/Even or Left/Right) | NA | |||