ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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8.4.5.2.1 Native Aux Transactions

Native Aux transaction is broken into two pieces: Request and Reply. The DSIx6 will always be the originator of the Request (sometimes under GPU control and other times under DSIx6 HW control) and the recipient of the Reply from the downstream device.

Request Syntax: <4-bit AUX_CMD> <20-bit AUX_ADDR> <7-bit AUX_LENGTH> <DATA0 … DATA15>

Reply Syntax: <4-bit AUX_CMD> <4’b0000> <DATA0 … DATA15>

Table 8-9 Definition of the AUX_CMD Field for Request Transactions
AUX_CMD[3:0]DESCRIPTION
0x0I2C-Over-Aux Write MOT = 0.
0x1I2C-Over-Aux Read MOT = 0
0x2I2C-Over-Aux Write Status Update MOT = 0.
0x3Reserved. DSIx6 will ignore.
0x4I2C-Over-Aux Write MOT = 1
0x5I2C-Over-Aux Read MOT = 1
0x6I2C-Over-Aux Write Status Update MOT=1.
0x7Reserved. SN65DSI86 will ignore.
0x8Native Aux Write
0x9Native Aux Read
0xA through 0xFReserved. SN65DSI86 will ignore.

For Native Aux Reply transactions, the DSIx6 will update the status field in the CFR with command provided by the eDP device. For example, if the eDP receiver replies with a AUX_DEFER, the DSIx6 will attempt the request seven times (100 µs between each attempt) before updating the AUX_DEFR status field with 1’b1. If the eDP receiver does NOT reply before the 400-µs reply timer times out, then the SN65DSI86 will wait 100 µs before trying the request again. The SN65DSI86 will retry the request 7 times before giving up and then update the AUX_RPLY_TOUT field with 1’b1.

Example: Native Aux read of the eDP receiver capability field at DCPD address 0x00000h through 0x00008

  1. Software programs the AUX_CMD field with 0x9.
  2. Software programs the AUX_ADDR[19:16] field with 0x0.
  3. Software programs the AUX_ADDR[15:8] field with 0x0.
  4. Software programs the AUX_ADDR[7:0] field with 0x0.
  5. Software programs the AUX_LENGTH field with 0x8.
  6. Software sets the SEND bit.
  7. DSIx6 will transmit the following packet: <SYNC> <0x90> <0x00> <0x00> <0x07> <STOP>
  8. Within 300 µs, the eDP receiver will reply with the following: <SYNC> <0x00> <DATA0> <DATA1> <DATA2> <DATA3> <DATA4> <DATA5> <DATA6> <DATA7> <STOP>
  9. DSIx6 will update AUX_RDATA0 through AUX_RDATA7 with the data received from the eDP receiver.
  10. DSIx6 will update the AUX_LENGTH field with 0x8 indicating eight bytes we received.
  11. DSIx6 will then clear the SEND bit.
  12. If enabled, the IRQ will be asserted to indicate to GPU that the Native Aux Read completed.
  13. GPU should read from the Interrupt Status register to see if the Native Aux Read completed successfully.
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