ZHCSPC1P February 2002 – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD10 , SN75HVD11 , SN75HVD12
PRODUCTION DATA
The differential receivers of the SN65HVD1x family are fail-safe to invalid bus states caused by:
In any of these cases, the differential receiver will output a fail-safe logic High state so that the output of the receiver is not indeterminate.
Receiver fail-safe is accomplished by offsetting the receiver thresholds, such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when VID is more negative than –200 mV. The receiver parameters which determine the fail-safe performance are VIT(+) and VIT(–). As shown in Section 7.6, differential signals more negative than –200 mV will always cause a Low receiver output, and differential signals more positive than +200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –10 mV, and the receiver output will be High.