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ZHCSWS8E September 2010 – October 2024 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

D|8
- MSOI002K

散热焊盘机械数据 (封装 | 引脚)

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5.8 Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
DRIVER (SN65HVD1780)
t_r, t_f	Driver differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3	3.15 V < V_CC < 3.45 V	0.4	1.4	1.8	μs
t_r, t_f	Driver differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3	3.15 V < V_CC < 5.5 V	0.4	1.7	2.6	µs
t_PHL, t_PLH	Driver propagation delay	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3			0.8	2	μs
t_SK(P)	Driver differential output pulse skew, \|t_PHL – t_PLH\|	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3			20	250	ns
t_PHZ, t_PLZ	Driver disable time	See Figure 6-4 and Figure 6-5			0.1	5	μs
t_PZH, t_PZL	Driver enable time	Receiver enabled	See Figure 6-4 and Figure 6-5		0.2	3	μs
t_PZH, t_PZL	Driver enable time	Receiver disabled	See Figure 6-4 and Figure 6-5		3	12	μs
DRIVER (SN65HVD1781)
t_r, t_f	Driver differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3		50		300	ns
t_PHL, t_PLH	Driver propagation delay	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3				200	ns
t_SK(P)	Driver differential output pulse skew, \|t_PHL – t_PLH\|	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3				25	ns
t_PHZ, t_PLZ	Driver disable time	See Figure 6-4 and Figure 6-5				3	μs
t_PZH, t_PZL	Driver enable time	Receiver enabled	See Figure 6-4 and Figure 6-5			300	ns
t_PZH, t_PZL	Driver enable time	Receiver disabled	See Figure 6-4 and Figure 6-5			10	μs
DRIVER (SN65HVD1782)
t_r, t_f	Driver differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF	All V_CC and Temp			50	ns
t_r, t_f	Driver differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF	V_CC > 4.5V and T < 105°C		16		ns
t_PHL, t_PLH	Driver propagation delay	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3				55	ns
t_SK(P)	Driver differential output pulse skew, \|t_PHL – t_PLH\|	R_L = 54 Ω, C_L = 50 pF, See Figure 6-3				10	ns
t_PHZ, t_PLZ	Driver disable time	See Figure 6-4 and Figure 6-5				3	μs
t_PZH, t_PZL	Driver enable time	Receiver enabled	See Figure 6-4 and Figure 6-5			300	ns
t_PZH, t_PZL	Driver enable time	Receiver disabled	See Figure 6-4 and Figure 6-5			9	μs
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
t_r, t_f	Receiver output rise/fall time ⁽¹⁾	C_L = 15 pF, See Figure 6-6	All devices		4	15	ns
t_PHL, t_PLH	Receiver propagation delay time	C_L = 15 pF, See Figure 6-6	HVD1780-Q1, HVD1781-Q1		100	200	ns
t_PHL, t_PLH	Receiver propagation delay time	C_L = 15 pF, See Figure 6-6	HVD1782-Q1			80	ns
t_SK(P)	Receiver output pulse skew, \|t_PHL – t_PLH\|	C_L = 15 pF, See Figure 6-6	HVD1780-Q1, HVD1781-Q1		6	20	ns
t_SK(P)	Receiver output pulse skew, \|t_PHL – t_PLH\|	C_L = 15 pF, See Figure 6-6	HVD1782-Q1			5	ns
t_PLZ, t_PHZ	Receiver disable time ⁽¹⁾	Driver enabled, See Figure 6-7			15	100	ns
t_PZL(1), t_PZH(1) t_PZL(2), t_PZH(2)	Receiver enable time	Driver enabled, See Figure 6-7			80	300	ns
t_PZL(1), t_PZH(1) t_PZL(2), t_PZH(2)	Receiver enable time	Driver disabled, See Figure 6-8			3	9	μs

(1) Specified by design. Not production tested.