ZHCSRU3J January   2008  – March 2023 SN65HVD1785 , SN65HVD1786 , SN65HVD1787 , SN65HVD1791 , SN65HVD1792 , SN65HVD1793

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Product Selection Guide
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-EF6E23B6-467E-4F27-83DC-9566F6730B27/SLLS8725683
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Thermal Considerations
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Hot-Plugging
      2. 9.3.2 Receiver Failsafe
      3. 9.3.3 70-V Fault-Protection
      4. 9.3.4 Additional Options
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Receiver Failsafe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.7 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER (HVD1785 AND HVD1791)
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF,
see Figure 8-3		 0.4 1.7 2.6 μs
tPHL, tPLH Driver propagation delay 0.8 2 μs
tSK(P) Driver differential output pulse skew,
|tPHL – tPLH|		 20 250 ns
tPHZ, tPLZ Driver disable time See Figure 8-4 and Figure 8-5 0.1 5 μs
tPZH, tPZL Driver enable time Receiver enabled 0.2 3 μs
Receiver disabled 3 12
DRIVER (HVD1786 AND HVD1792)
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF,
see Figure 8-3		 50 300 ns
tPHL, tPLH Driver propagation delay 200 ns
tSK(P) Driver differential output pulse skew,
|tPHL – tPLH|		 25 ns
tPHZ, tPLZ Driver disable time See Figure 8-4 and Figure 8-5 3 μs
tPZH, tPZL Driver enable time Receiver enabled 300 ns
Receiver disabled 10 μs
Receiver enabled VCM > VCC 500 ns
DRIVER (HVD1787 AND HVD1793)
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF,
see Figure 8-3		 3 30 ns
tPHL, tPLH Driver propagation delay 50 ns
tSK(P) Driver differential output pulse skew,
|tPHL – tPLH|		 10 ns
tPHZ, tPLZ Driver disable time See Figure 8-4 and Figure 8-5 3 μs
tPZH, tPZL Driver enable time Receiver enabled 300 ns
Receiver disabled 9 μs
Receiver enabled VCM > VCC 500 ns
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
tr, tf Receiver output rise/fall time CL = 15 pF,
see Figure 8-6		 4 15 ns
tPHL, tPLH Receiver propagation delay time 85, 86, 91, 92 100 200 ns
87, 93 70
tSK(P) Receiver output pulse skew,
|tPHL – tPLH|		 85, 86, 91, 92 6 20 ns
87, 93 5
tPLZ, tPHZ Receiver disable time Driver enabled, see Figure 8-7 15 100 ns
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)		 Receiver enable time Driver enabled, see Figure 8-7 80 300 ns
Driver disabled, see Figure 8-8 3 9 μs
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