ZHCSDL3O MARCH 2001 – April 2018 SN65HVD230 , SN65HVD231 , SN65HVD232
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
t(LOOP1) | Total loop delay, driver input to receiver output, recessive to dominant | V(Rs) = 0 V, | See Figure 26 | 70 | 115 | ns | |
RS with 10 kΩ to ground, | See Figure 26 | 105 | 175 | ||||
RS with 100 kΩ to ground, | See Figure 26 | 535 | 920 | ||||
t(LOOP2) | Total loop delay, driver input to receiver output, dominant to recessive | V(Rs) = 0 V, | See Figure 26 | 100 | 135 | ns | |
RS with 10 kΩ to ground, | See Figure 26 | 155 | 185 | ||||
RS with 100 kΩ to ground, | See Figure 26 | 830 | 990 |