11.1 Application Information

The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus state is when the bus is biased to V_CC / 2 via the high-resistance internal resistors R_IN and R_ID of the receiver, corresponding to a logic high on the D and R pins. See Figure 34 and Figure 35.

Figure 34. Bus States (Physical Bit Representation)

Figure 35. Simplified Recessive Common Mode Bias and Receiver

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the link layer portion of the CAN protocol. The different nodes on the network are typically connected through the use of a 120-Ω characteristic impedance twisted-pair cable with termination on both ends of the bus.