ZHCSRQ1M september 2005 – february 2023 SN65HVD30 , SN65HVD31 , SN65HVD32 , SN65HVD33 , SN65HVD34 , SN65HVD35
PRODUCTION DATA
The differential receivers of the SN65HVD3x family are failsafe to invalid bus states caused by:
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–. As shown in the Electrical Characteristics table, differential signals more negative than –200 mV always cause a low receiver output, and differential signals more positive than 200 mV always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output is high. Only when the differential input is more than VHYS below VIT+ does the receiver output transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver hysteresis value (VHYS) as well as the value of VIT+.