When the driver enable pin (DE) is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as V_OD = V_A – V_B is positive. When D is low, the output states reverse, B turns high, A is low, and V_OD is negative.

When DE is low, both outputs turn high impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground; thus when left open, the driver is disabled (high impedance) by default. The D pin has an internal pullup resistor to VCC; thus when left open while the driver is enabled, output A turns high and B turns low.

When the receiver enable pin ( RE) is logic low, the receiver is enabled. When the differential input voltage defined as V_ID = V_A – V_B is positive and higher than the positive input threshold (V_IT+) the receiver output (R) turns high. When V_ID is negative and lower than the negative input threshold (V_IT–), the receiver output (R) turns low. If V_ID is between V_IT+ and V_IT–, the output is indeterminate.

When RE is logic high or left open, the receiver output is high impedance and the magnitude and polarity of V_ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

Figure 8-1 Equivalent Input and Output Schematic Diagrams