ZHCSB94C July   2013  – January 2018 SN65HVD888

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      支持极性纠正 (POLCOR) 的典型网络应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: JEDEC Specifications
    3. 6.3 ESD Ratings: IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Driver
    2. 7.2 Receiver
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Standby Mode
      2. 8.3.2 Bus Polarity Correction
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Configuration
      2. 9.1.2 Bus Design
      3. 9.1.3 Cable Length Versus Data Rate
      4. 9.1.4 Stub Length
      5. 9.1.5 3- to 5-V Interface
      6. 9.1.6 Noise Immunity
      7. 9.1.7 Transient Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Design and Layout Considerations For Transient Protection
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.8 Switching Characteristics

3.3 ms > bit time > 4 μs (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DRIVER
tr, tf Driver differential-output rise and fall times RL = 54 Ω, CL = 50 pF See Figure 6 400 700 1200 ns
tPHL, tPLH Driver propagation delay RL = 54 Ω, CL = 50 pF See Figure 6 90 700 1000 ns
tSK(P) Driver pulse skew, |tPHL – tPLH| RL = 54 Ω, CL = 50 pF See Figure 6 25 200 ns
tPHZ, tPLZ Driver disable time See Figure 7 and Figure 8 50 500 ns
tPHZ, tPLZ Driver enable time Receiver enabled See Figure 7 and Figure 8 500 1000 ns
Receiver disabled See Figure 7 and Figure 8 3 9 µs
RECEIVER
tr, tf Receiver output rise and fall times CL = 15 pF See Figure 9 18 30 ns
tPHL, tPLH Receiver propagation delay time CL = 15 pF See Figure 9 85 195 ns
tSK(P) Receiver pulse skew, |tPHL – tPLH| CL = 15 pF See Figure 9 1 15 ns
tPHZ, tPLZ Receiver disable time 50 500
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)		 Receiver enable time Driver enabled See Figure 10 20 130 ns
Driver disabled See Figure 11 2 8 µs
tFS Bus failsafe time Driver disabled See Figure 12 44 58 76 ms
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