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ZHCS603D November 2011 – April 2022 SN65HVDA100-Q1

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D|8
- MSOI002K

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7.5 Electrical Characteristics

V_SUP = 5V to 27 V, T_J = –40°C to 150°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
V_SUP SUPPLY
V_SUP	Operational supply voltage (ISO 17987-4 Param 10)⁽²⁾		5	14	27	V
V_SUP	Nominal supply voltage (ISO 17987-4 Param 10)	Normal and standby modes	7	14	18	V
V_SUP	Nominal supply voltage (ISO 17987-4 Param 10)	Sleep mode	7	12	18	V
UV_SUP	Undervoltage V_SUP threshold		4.35		4.65	V
UV_HYS	Delta hysteresis voltage for V_SUP undervoltage threshold			0.2		V
I_SUP	Supply current	Normal mode, EN = high, Bus dominant (total bus load where R_LIN ≥ 500 Ω and C_LIN ≤ 10 nF (see Figure 8-1 )⁽³⁾, INH = V_SUP, NWake = V_SUP		1.2	7.5	mA
		Standby mode, EN = low, Bus dominant (total bus load where R_LIN ≥ 500 Ω and C_LIN ≤ 10 nF (see Figure 8-1)⁽³⁾, INH = V_SUP, NWake = V_SUP		1	2.1	mA
		Normal mode, EN = high, Bus recessive, LIN = V_SUP, INH = V_SUP, NWake = V_SUP		450	775	μA
		Standby mode, EN = low, Bus recessive, LIN = V_SUP, INH = V_SUP, NWake = V_SUP		450	775	μA
		Sleep mode, 7 V < V_SUP ≤ 14 V, LIN = V_SUP, NWake = V_SUP, EN = 0 V, TXD and RXD floating		10	20	μA
		Sleep mode, 14 V < V_SUP < 27 V, LIN = V_SUP, NWake = V_SUP, EN = 0 V, TXD and RXD floating			30	μA
RXD OUTPUT PIN (OPEN DRAIN)
V_O	Output voltage⁽⁴⁾		–0.3		5.5	V
I_OL	Low-level output current, open drain	LIN = 0 V, RXD = 0.4 V	3.5			mA
I_IKG	Leakage current, high-level	LIN = V_SUP, RXD = 5 V	–5	0	5	μA
TXD INPUT/OUTPUT PIN
V_IL	Low-level input voltage		–0.3		0.8	V
V_IH	High-level input voltage		2		5.5	V
V_IT	Input threshold hysteresis voltage		30		500	mV
	Pulldown resistor		125	350	800	kΩ
I_IL	Low-level input leakage current	TXD = Low	–5	0	5	μA
I_{TXD_Wake}	Local wake up source re recognition TXD open drain drive	Standby mode after a local wake up event, V_LIN = V_SUP, NWake = 0 V, TXD = 1 V	1.3	4.6	8	mA
LIN PIN (REFERENCED TO V_SUP)
V_OH	High-level output voltage	LIN recessive, TXD = high, I_O = 0 mA, V_SUP = 14 V	V_SUP – 1			V
V_OL	Low-level output voltage	LIN dominant, TXD = low, I_O = 40 mA, V_SUP = 14 V			0.2 × V_SUP	V
I_L	Limiting current (ISO 17987-4 Param 12)	TXD = 0 V, V_LIN = 7 V to 27 V	40	90	200	mA
I_LKG	Receiver leakage current, dominant (ISO 17987-4 Param 13)	LIN = 0 V, 7 V ≤V_SUP ≤ 18 V, Driver off	–1			mA
	Receiver leakage current, recessive (ISO 17987-4 Param 14)	LIN ≥ V_SUP, 7 ≤ V_SUP ≤18 V, Driver off			20	μA
	Receiver leakage current, recessive (ISO 17987-4 Param 14)	LIN = V_SUP, driver off	–5		5	μA
I_LKG	Leakage current, loss of ground (ISO 17987-4 Param 15)	GND = V_SUP , V_SUP = 12 V, 0 V < VLIN < 18 V	–1		1	mA
I_LKG	Leakage current, loss of supply (ISO 17987-4 Param 16)	7 V < LIN ≤ 12 V, V_SUP = GND			5	μA
I_LKG	Leakage current, loss of supply (ISO 17987-4 Param 16)	12 V < LIN ≤ 18 V, V_SUP = GND			10	μA
V_IL	Low-level input voltage (ISO 17987-4 Param 17)	LIN dominant (including LIN dominant for wake up)			0.4 × V_SUP	V
V_IH	High-level input voltage (ISO 17987-4 Param 18)	LIN recessive	0.6 × V_SUP			V
V_{BUS_CNT}	Receiver center threshold (ISO 17987-4 Param 19)	V_{BUS_CNT} = (V_IL + V_IH) / 2	0.475 x V_SUP	0.5 × V_SUP	0.525 x V_SUP	V
V_HYS	Hysteresis voltage (ISO 17987-4 Param 20)	V_HYS = (V_IL - V_IH)	0.05 × V_SUP		0.175 × V_SUP	V
V_{SERIAL_ DIODE}	Serial diode in LIN termination pull up path (ISO 17987-4 Param 21)	By design and characterization	0.4	0.7	1.0	V
R_RESPONDER	Pullup resistor to V_SUP (ISO 17987-4 Param 26)	Normal and standby modes	20	30	60	kΩ
R_SLEEP	Pullup current source to V_SUP	Sleep mode, V_SUP = 14 V, LIN = GND	–2		–20	μA
EN INPUT PIN
V_IL	Low-level input voltage		–0.3		0.8	V
V_IH	High-level input voltage		2		5.5	V
V_hys	Hysteresis voltage	By design and characterization	30		500	mV
	Pulldown resistor		125	350	800	kΩ
I_IL	Low-level input current	EN = Low	–5	0	5	μA
INH OUTPUT PIN
R_DS(on)	ON-state resistance	Between V_SUP and INH, INH = 2-mA drive, Normal or standby mode		25	50	Ω
I_IKG	Leakage current	Low-power mode, 0 < INH < V_SUP	–5	0	5	μA
NWAKE INPUT PIN
V_IL	Low-level input voltage		–0.3		V_SUP – 3.3	V
V_IH	High-level input voltage		V_SUP – 1		V_SUP + 0.3	V
	Pullup current	NWake = 0 V	–45	–10	–2	μA
I_IKG	Leakage current	V_SUP = NWake	–5	0	5	μA
AC CHARACTERISTICS
D1	Duty cycle 1⁽⁵⁾ (ISO 17987-4 Param 27)	TH_REC(max) = 0.744 × V_SUP, TH_DOM(maximum) = 0.581 × V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50 μs (20 kbps), D1 = t_{Bus_rec(min)}/ (2 × t_BIT) (see Figure 7-1)	0.396
D2	Duty cycle 2⁽⁵⁾ (ISO 17987-4 Param 28)	TH_REC(min) = 0.422 × V_SUP, TH_DOM(min) = 0.284 × V_SUP, V_SUP = 7.6 V to 18 V, t_BIT = 50 μs (20 kbps), D2 = t_{Bus_rec(max)}/ (2 × t_BIT) (see Figure 7-1)			0.581
D3	Duty cycle 3⁽⁵⁾ (ISO 17987-4 Param 29)	TH_REC(max) = 0.778 × V_SUP, TH_DOM(max) = 0.616 × V_SUP, V_SUP = 7 V to 18 V, t_BIT = 96 μs (10.4 kbps), D3 = t_{Bus_rec(min)}/ (2 × t_BIT) (see Figure 7-1)	0.417
D4	Duty cycle 4⁽⁵⁾ (ISO 17987-4 Param 30)	TH_REC(min) = 0.389 × V_SUP, TH_DOM(min) = 0.251 × V_SUP, V_SUP = 7.6 V to 18 V, t_BIT = 96 μs (10.4 kbps), D4 = t_{Bus_rec(max)}/ (2 × t_BIT) (see Figure 7-1)			0.59

(1) Typical values are given for V_SUP = 14 V at 25°C, except for low power mode where typical values are given for V_SUP = 12 V at 25°C.

(2) All voltages are defined with respect to ground; positive currents flow into the SN65HVDA100-Q1 device.

(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:I_SUP _{(dom) max termination} ≉ (V_SUP – (V_{LIN_Dominant} + 0.7 V) / 20 kΩ.

(4) RXD pin output is open drain. Output voltage is through external pullup resistance to logic supply of the system and impedance of the RXD pin.

(5) Duty cycles: LIN driver bus load conditions (C_LINBUS, R_LINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The SN65HVDA100-Q1 also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification.