ZHCSFW5 December 2016 SN65LBC175A-EP
PRODUCTION DATA.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Supply voltage, VCC(2) | –0.3 | 6 | V | ||
| Voltage at any bus input (steady state), A and B | –10 | 15 | V | ||
| Voltage at any bus (transient pulse through 100 Ω, see Figure 10) | –30 | 30 | V | ||
| Input voltage at 1,2EN and 3,4EN, VI | –0.5 | VCC + 0.5 | V | ||
| Receiver output current, IO | –10 | 10 | mA | ||
| Storage temperature, Tstg | –65 | 150 | °C | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to GND and are steady-state (unless otherwise specified).
6.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | A and B to GND | ±6000 | V |
| All pins | ±5000 | ||||
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | All pins | ±2000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VCC | Supply voltage | 4.75 | 5 | 5.25 | V | |
| Voltage at any bus terminal | A, B | –7 | 12 | V | ||
| VIH | High-level input voltage | EN | 2 | VCC | V | |
| VIL | Low-level input voltage | 0 | 0.8 | V | ||
| Output current | Y | –8 | 8 | mA | ||
| TJ | Junction temperature | –55 | 125 | °C | ||
6.4 Thermal Information
| THERMAL METRIC(1) | SN65LBC175A-EP | UNITS | |
|---|---|---|---|
| D (SOIC) | |||
| 16 PINS | |||
| θJA | Junction-to-ambient thermal resistance | 78 | °C/W |
| θJCtop | Junction-to-case (top) thermal resistance | 39.5 | °C/W |
| θJB | Junction-to-board thermal resistance | 35.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 8.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 35.1 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
over recommended operating conditions| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VIT+ | Positive-going differential input voltage threshold | –7 V ≤ VCM ≤ 12 V (VCM = (VA + VB) / 2) | –80 | –10 | mV | |||
| VIT- | Negative-going differential input voltage threshold | –200 | –120 | mV | ||||
| VHYS | Hysteresis voltage (VIT+ – VIT–) | –40 | mV | |||||
| VIK | Input clamp voltage | II = –18 mA | –1.5 | –0.8 | V | |||
| VOH | High-level output voltage | VID = 200 mV, IOH = –8 mA |
See Figure 6 | 2.7 | 4.8 | V | ||
| VOL | Low-level output voltage | VID = –200 mV, IOL = 8 mA |
0.2 | 0.4 | V | |||
| IOZ | High-impedance-state output current | VO = 0 V to VCC | –1 | 1 | µA | |||
| II | Line input current | Other input at 0 V, VCC = 0 V or 5 V |
VI = 12 V | 0.9 | mA | |||
| VI = –7 V | –0.7 | |||||||
| IIH | High-level input current | Enable inputs | 110 | µA | ||||
| IIL | Low-level input current | –100 | µA | |||||
| RI | Input resistance | A, B inputs | 12 | kΩ | ||||
| ICC | Supply current | VID = 5 V | 1,2EN, 3,4EN at 0 V | 32 | µA | |||
| No load | 1,2EN, 3,4EN at VCC | 11 | 16 | mA | ||||
(1) All typical values are at VCC = 5 V and 25°C.
6.6 Switching Characteristics
Over recommended operating conditions| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tr | Output rise time | VID = –3 V to 3 V, See Figure 7 |
2 | 7 | ns | ||
| tf | Output fall time | 2 | 7 | ns | |||
| tPLH | Propagation delay time, low-to-high level output | 8 | 12 | 18 | ns | ||
| tPHL | Propagation delay time, high-to-low level output | 8 | 12 | 18 | ns | ||
| tPZH | Propagation delay time, high-impedance to high-level output | See Figure 8 | 27 | 39 | ns | ||
| tPHZ | Propagation delay time, high-level-output to high-impedance | 7 | 24 | ns | |||
| tPZL | Propagation delay time, high-impedance to low-level output | See Figure 9 | 29 | 39 | ns | ||
| tPLZ | Propagation delay time, low-level-output to high-impedance | 12 | 18 | ns | |||
| tsk(p) | Pulse skew (|tPLH – tPHL|) | 0.2 | 2 | ns | |||
| tsk(o) | Output skew(1) | 3 | ns | ||||
| tsk(pp) | Part-to-part skew(2) | 3 | ns | ||||
(1) Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
(2) Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits.
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. Enhanced plastic product disclaimer applies.
Figure 1. SN65LBC175A-EP Wirebond Life Derating Chart
6.7 Typical Characteristics
| VCC = 5 V | TA = 25°C |
