9.3.1 Power Down

Use a 5-kΩ pullup for normal operation. To power down the SN65LVCP114, tie this pin to GND. In power-down mode, Inputs are off, outputs are disabled, and I²C is reset. Power-down mode can be set, writing a 1 to register 0x00 bit 6.

9.3.2 Lane Enable

Each lane can be enabled individually using pin LN_x_EN or register 0x12[3:0]. This enables lane x for all ports.

9.3.3 Gain and Equalization

Equalization can be configured using EQx[1:0] pins or registers 0x03[3:0], 0x07[3:0], and 0x0B[3:0]. The SN65LVCP114 device includes several possible equalizations to select the optimum value. Also, the GAINx pin or registers 0x04[1:0], 0x08[1:0], and 0x0C[1:0] can be used to attenuate the input signal.

If input swing is larger than 600 mVpp, set gain to 0.5. Otherwise, set gain to 1.

9.3.4 VOD

Output swing can be selected between two ranges with an associated gain. Notice the range sets a maximum value not a constant value.

9.3.5 AGC

When AGC is enabled, the part-to-part gain variation can be reduced. AGC can be disabled for each port through DIS_AGCx or registers 0x02[0], 0x06[0], and 0x0A[0].

9.3.6 GPIO or I²C Configuration

To configure this device using GPIO, set I2C_SEL = LOW. Using GIO, you have access to the most of the configuration, to power down the device, control equalization, select port, select VOD range, set loop-back mode, set diagnostic mode, enable lanes, enable AGC, select gain, and enable fast switching.

To configure this device using I²C set I2C_SEL = HIGH. Besides the configuration you have with GPIO, using I²C allows you to disable outputs, power-down inputs and switch polarity of outputs. In this mode, use pins ADDx to set I²C address. See Programming for a detailed explanation.

9.3.7 Fast Switching

Idle outputs can be disabled or squelched. When outputs are squelched, switching is faster; when outputs are disabled, power is saved. This configuration is done with the FST_SW pin or registers 0x02[3], 0x06[3], and 0x0A[3].

9.3.8 Power-Down Input Stages

Each port can power down its input stages to save power when not used. Power down affects all the lanes of the port; to configure it, use registers 0x03[7], 0x07[7], and 0x08[7] for port A, B, and C respectively.

9.3.9 Disable Output Lanes

The SN65LVCP114 device can disable every output lane independently. Use register 0x02[7:4] to disable output lanes of port A, register 0x06[7:4] to disable output lanes of port B, and register 0x0A[7:4] to disable output lanes of port C.

9.3.10 Polarity Switch

Every lane can switch its polarity independently. Port A is configured through register 0x10[3:0], port B is configured through register 0x10[7:4], and port C is configured through register 0x11[3:0]. See Table 16 for a detailed explanation.

9.4.1 Normal Mode

In this mode, the SN65LVCP114 functions like a switch. C port will connect to A or B port depending on values of SELx or register 0x01[3:0], each lane is configured independently.

9.4.2 Loopback

In loopback mode, the selected port transmits on its output what it is receiving on its input. Each port has independent loopback configuration. This configuration can be selected using the LPx pins or register 0x01[6:4]. See Figure 14 for a graphical representation.

9.4.3 Diagnostic

When in diagnostic mode, data incoming on port C is reflected in both A and B ports. Data outgoing on port C depends on the value of SELx. This mode can be selected using DIAG pin or register 0x01[7]. See Figure 15 for a graphical representation.

9.5.1 Two-Wire Serial Interface and Control Logic

The SN65LVCP114 device uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCL pins require external 10-kΩ pullups to V_CC.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out the control signals. The SN65LVCP114 device is a slave device only, which means that it cannot initiate a transmission itself; it always relies on the availability of the SCL signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data transmission is as follows:

1. START command
2. 7-bit slave address (0000ADD[2:0]) followed by an 8th bit which is the data direction bit (R/W). A zero indicates a WRITE and a 1 indicates a READ. The ADD[2:0] address bits change with the status of the ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7-bit slave address is 0000000.
3. 8-bit register address
4. 8-bit register data word
5. STOP command

Regarding timing, the SN65LVCP114 device is I²C compatible. Figure 16 shows the typical timing, and Figure 17 shows the data transfer. Table 15 defines the parameters forFigure 16.

Bus Idle: Both SDA and SCL lines remain HIGH

Start data transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition (S). Each data transfer is initiated with a START condition.

Stop Data Transfer:A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still must communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line, and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be considered. When a slave-receiver does not acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition.

Figure 16. Two-Wire Serial Interface Timing Diagram

Figure 17. Two-Wire Serial Interface Data Transfer

9.6.1 SN65LVCP114 Register Mapping Information