SLLS362G SEPTEMBER   1999  – January 2016 SN65LVDS387 , SN65LVDS389 , SN65LVDS391 , SN75LVDS387 , SN75LVDS389 , SN75LVDS391

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Driver Output Voltage and Power-On Reset
      2. 10.3.2 5-V Input Tolerance
      3. 10.3.3 NC Pins
      4. 10.3.4 Unused Enable Pins
      5. 10.3.5 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Signaling Rate vs Distance
    2. 11.2 Typical Application
      1. 11.2.1 Point-to-Point Communications
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Driver Supply Voltage
          2. 11.2.1.2.2 Driver Bypass Capacitance
          3. 11.2.1.2.3 Driver Output Voltage
          4. 11.2.1.2.4 Interconnecting Media
          5. 11.2.1.2.5 PCB Transmission Lines
          6. 11.2.1.2.6 Termination Resistor
          7. 11.2.1.2.7 Driver NC Pins
        3. 11.2.1.3 Application Curve
      2. 11.2.2 Multidrop Communications
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
          1. 11.2.2.2.1 Interconnecting Media
        3. 11.2.2.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
      2. 14.1.2 Other LVDS Products
    2. 14.2 Documentation Support
      1. 14.2.1 Related Information
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
  • DGG|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, VCC(2) –0.5 4 V
Input voltage range Inputs –0.5 6 V
Y or Z –0.5 4 V
Continuous power dissipation See Thermal Information
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds 260 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge SN65' (Y, Z, and GND) Class 3, A ±15000 V
Class 3, B ±400 V
SN75' (Y, Z, and GND) Class 3, A ±4000 V
Class 3, B ±400 V
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds 260 °C

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
TA Operating free-air temperature SN75' 0 70 °C
SN65' –40 85 °C

8.4 Thermal Information

THERMAL METRIC(1) SN65LVDS387 SN75LVDS389 SN75LVDS387 SN65LVDS391 SN65LVDS389 SN75LVDS391 UNIT
DGG DBT D PW
64 PINS 38 PINS 16 PINS 16 PINS
Derating Factor Above TA = 25°C(2) 16.7 8.5 7.6 6.2 mW/°C
Power Rating: TA≤ 25°C 2094 1071 950 774 mW
Power Rating: TA = 70°C 1342 688 608 496
Power Rating: TA = 85°C 1089 556 494 402
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.

8.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
|VOD| Differential output voltage magnitude RL = 100 Ω,
See Figure 9 and Figure 10		 247 340 454 mV
Δ|VOD| Change in differential output voltage magnitude between logic states –50 50
VOC(SS) Steady-state common-mode output voltage See Figure 11 1.125 1.375 V
ΔVOC(SS) Change in steady-state common-mode output voltage between logic states –50 50 mV
VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV
ICC Supply current 'LVDS387 Enabled, RL = 100 Ω,
VIN = 0.8 V or 2 V		 85 95 mA
'LVDS389 50 70
'LVDS391 20 26
'LVDS387 Disabled,
VIN = 0 V or VCC		 0.5 1.5
'LVDS389 0.5 1.5
'LVDS391 0.5 1.3
IIH High-level input current VIH = 2 V 3 20 µA
IIL Low-level input current VIL = 0.8 V 2 10 µA
IOS Short-circuit output current VOY or VOZ = 0 V ±24 mA
VOD = 0 V ±12 mA
IOZ High-impedance output current VO = 0 V or VCC ±1 µA
IO(OFF) Power-off output current VCC = 1.5 V, VO = 2.4 V ±1 µA
CIN Input capacitance VI = 0.4sin(4E6πt) + 0.5 V 5 pF
CO Output capacitance VI = 0.4sin(4E6πt) + 0.5 V, Disabled 9.4 pF
(1) All typical values are at 25°C and with a 3.3-V supply.

8.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output RL = 100 Ω,
CL = 10 pF,
See Figure 12		 0.9 1.7 2.9 ns
tPHL Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns
tr Differential output signal rise time 0.4 0.8 1 ns
tf Differential output signal fall time 0.4 0.8 1 ns
tsk(p) Pulse skew (|tPHL – tPLH|) 150 500 ps
tsk(o) Output skew(2) 80 150 ps
tsk(pp) Part-to-part skew(3) 1.5 ns
tPZH Propagation delay time, high-impedance-to-high-level output See Figure 13 6.4 15 ns
tPZL Propagation delay time, high-impedance-to-low-level output 5.9 15 ns
tPHZ Propagation delay time, high-level-to-high-impedance output 3.5 15 ns
tPLZ Propagation delay time, low-level-to-high-impedance output 4.5 15 ns
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.

8.7 Typical Characteristics

SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_lvds391_lls362.gif Figure 1. 'LVDS391 Supply Current vs (RMS) Switching Frequency
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_lvds389_lls362.gif Figure 3. 'LVDS389 Supply Current (RMS) vs Switching Frequency
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_hi_lo_lls362.gif Figure 5. High-to-Low Propagation Delay Time vs Free-Air Temperature
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_hi_lev_lls362.gif Figure 7. High-Level Output Voltage vs High-Level Output Current
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_lvds387_lls362.gif Figure 2. 'LVDS387 Supply Current (RMS) vs Switching Frequency
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_lo_hi_lls362.gif Figure 4. Low-to-High Propagation Delay Time vs Free-Air Temperature
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_lo_lev_lls362.gif Figure 6. Low-Level Output Voltage vs Low-Level Output Current
SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 tc_outp_lls362.gif Figure 8. Output Voltage vs Time
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