9.2.2.1 Power Up Sequence

The SN65LVDS93A-Q1 does not require a specific power up sequence.

It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while all other device blocks are still powered down.

It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still lower than normal mode.

The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended:

Power up sequence (SN65LVDS93A-Q1 SHTDN input initially low):

1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle SN65LVDS93A-Q1 shutdown to SHTDN = V_IH.
5. Send >1ms of black video data; this allows the SN65LVDS93A-Q1 to be phase locked, and the display to show black data first.
6. Start sending true image data.
7. Enable backlight.

Power Down sequence (SN65LVDS93A-Q1 SHTDN input initially high):

1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times.
3. Set SN65LVDS93A-Q1 input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.

9.2.2.2 Signal Connectivity

While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how each signal should be connected from the graphic source through the SN65LVDS93A-Q1 input, output and LVDS LCD panel input. Detailed notes are provided with each figure.

Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD display data sheet.

• Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the dominate data format for LCD panels.
• Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.

Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.

• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.

Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93A-Q1 inputs must be tied to a valid logic level.

Figure 15. 24-Bit Color Host to 24-Bit LCD Panel Application

Note A. Leave output Y3 NC.

Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.

• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 16. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application

Note A. Leave output Y3 N.C.

Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect D0, D7, and D15 to VCC.

Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.

• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application

Note A. Leave output Y3 NC.

Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down to18-bit per pixel.

NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.

• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 18. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application

9.2.2.3 PCB Routing

Figure 19 shows a possible breakout of the data input and output signals on two layers of a printed circuit board.

Figure 19. Printed Circuit Board Routing Example (See Figure 14 for the Schematic)